Received: by 2002:ac0:b08d:0:0:0:0:0 with SMTP id l13csp4143271imc; Sun, 24 Feb 2019 22:52:50 -0800 (PST) X-Google-Smtp-Source: AHgI3IZgkHpVlufvBOo/9R3ZRZMVPzmgBZzCHBNO7ihaK7yW7Fa08gmwwKUg4CZ5eulgxJ0K2pqW X-Received: by 2002:a63:61c9:: with SMTP id v192mr17828060pgb.120.1551077570689; Sun, 24 Feb 2019 22:52:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551077570; cv=none; d=google.com; s=arc-20160816; b=i55eBBPzXnU3+1iXuHDPdlzPrxp0yxFgd7RdUwQ9ehNL5OLz568Fu8ChxD3+icEcl/ PHKKH5EQ+KJvZ93nD7DYrKKfMp0ah8QmLTOl2toiznjwngsa1UnY6RyLm01fFoqtTTPQ kFlzPG1R4hRpitNQ9/J/EV5AXElBWxo2N0S54sjakaDtq5aWQEPNEqPCsaFV46QpHLKk ElHJCY/bQu6BOxoho4iziLYjbJooQunGfz6NEf1+fQpapSMRoWPzre9j+T+JUrCgDowi hvFSekqTDK9xvf/+vCY27oiNX8PUTsooGoUH5acwz0pBeYs2z7VpT7yi34gcqGQL+UjC B2jA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=TAjIJ2Oprp9CFLIuGZLQThKZGxYNbc+IIKmp+waZceA=; b=H8X5A2QM58aMlcWPolkNsTbTsCHHGS4gZd/J3M1Po5BVexft5R0R9ilCF2wnNB32ZR o4ovXUMM38WRN1cBX1dZIGvuHcRtr3ccE/Y0Hpsgg7NH7KCIamUa0x7Tt4qyy9Whr+xG QOqyg/yW5PrVCIfIuWcxwL74AUlqBGfD6r8RfaTT4NeSm8LqouPaWBQB9VobvNbajxNH 182iDGTaeqPStMCqX6HzhCiHYILPk4MLi+7Sy104JT0TlrPcrosOvNFowQqC+IX/N3LS vyn+/GrF19kvLcmgl9fdSEeYKWDcLib3Pk/+DZbTlZwKZbtBpFNvYoaCsZcGgcll3bmL 3Z6Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u1si8415402pgn.158.2019.02.24.22.52.35; Sun, 24 Feb 2019 22:52:50 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728710AbfBYGvk (ORCPT + 99 others); Mon, 25 Feb 2019 01:51:40 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:20942 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728599AbfBYGvk (ORCPT ); Mon, 25 Feb 2019 01:51:40 -0500 X-UUID: 80d3c176059341c3a442300162d1536b-20190225 X-UUID: 80d3c176059341c3a442300162d1536b-20190225 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1613397474; Mon, 25 Feb 2019 14:51:25 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 25 Feb 2019 14:51:21 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 25 Feb 2019 14:51:21 +0800 From: Seiya Wang To: Stephen Boyd , Mark Rutland , Matthias Brugger , Michael Turquette , Rob Herring CC: , , , , , Seiya Wang Subject: [PATCH v2 2/2] clk: mediatek: correct cpu clock name for MT8173 SoC Date: Mon, 25 Feb 2019 14:51:12 +0800 Message-ID: <20190225065112.3400-2-seiya.wang@mediatek.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20190225065112.3400-1-seiya.wang@mediatek.com> References: <20190225065112.3400-1-seiya.wang@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Correct cpu clock name from ca57 to ca72 since MT8173 does use cortex-a72. Signed-off-by: Seiya Wang Reviewed-by: Matthias Brugger Acked-by: Stephen Boyd --- drivers/clk/mediatek/clk-mt8173.c | 4 ++-- include/dt-bindings/clock/mt8173-clk.h | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c index 96c292c3e440..deedeb3ea33b 100644 --- a/drivers/clk/mediatek/clk-mt8173.c +++ b/drivers/clk/mediatek/clk-mt8173.c @@ -533,7 +533,7 @@ static const char * const ca53_parents[] __initconst = { "univpll" }; -static const char * const ca57_parents[] __initconst = { +static const char * const ca72_parents[] __initconst = { "clk26m", "armca15pll", "mainpll", @@ -542,7 +542,7 @@ static const char * const ca57_parents[] __initconst = { static const struct mtk_composite cpu_muxes[] __initconst = { MUX(CLK_INFRA_CA53SEL, "infra_ca53_sel", ca53_parents, 0x0000, 0, 2), - MUX(CLK_INFRA_CA57SEL, "infra_ca57_sel", ca57_parents, 0x0000, 2, 2), + MUX(CLK_INFRA_CA72SEL, "infra_ca72_sel", ca72_parents, 0x0000, 2, 2), }; static const struct mtk_composite top_muxes[] __initconst = { diff --git a/include/dt-bindings/clock/mt8173-clk.h b/include/dt-bindings/clock/mt8173-clk.h index 8aea623dd518..76e4e5b65353 100644 --- a/include/dt-bindings/clock/mt8173-clk.h +++ b/include/dt-bindings/clock/mt8173-clk.h @@ -194,7 +194,8 @@ #define CLK_INFRA_PMICWRAP 11 #define CLK_INFRA_CLK_13M 12 #define CLK_INFRA_CA53SEL 13 -#define CLK_INFRA_CA57SEL 14 +#define CLK_INFRA_CA57SEL 14 /* Deprecated. Don't use it. */ +#define CLK_INFRA_CA72SEL 14 #define CLK_INFRA_NR_CLK 15 /* PERI_SYS */ -- 2.14.1