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From:   Parshuram Raju Thombare <pthombar@cadence.com>
To:     Andrew Lunn <andrew@lunn.ch>
CC:     "nicolas.ferre@microchip.com" <nicolas.ferre@microchip.com>,
        "davem@davemloft.net" <davem@davemloft.net>,
        "netdev@vger.kernel.org" <netdev@vger.kernel.org>,
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        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Rafal Ciepiela <rafalc@cadence.com>,
        Piotr Sroka <piotrs@cadence.com>, Jan Kotas <jank@cadence.com>
Subject: RE: [PATCH 2/3] net: ethernet: add c45 PHY support in MDIO read/write
 functions.
Thread-Topic: [PATCH 2/3] net: ethernet: add c45 PHY support in MDIO
 read/write functions.
Thread-Index: AQHUyur7TcFel7TGu0Sk9cKMaw0yw6XsWPMAgACSKrCAAJZkAIACrOPw
Date:   Mon, 25 Feb 2019 08:18:57 +0000
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>> >On Fri, Feb 22, 2019 at 08:12:42PM +0000, Parshuram Thombare wrote:
>> >> This patch modify MDIO read/write functions to support
>> >> communication with C45 PHY in Cadence ethernet controller driver.
>> >
>> >Hi Parshuram
>> >
>> >Are all versions of the MDIO controller capable of doing C45?
>> >
>> >    Andrew
>> Now driver support c22 and c45 PHY.
>> Are you suggesting to add check for C45 PHY using is_c45 in phydev ?
>
>You are unconditionally supporting C45. Are there versions of the hardware=
 which
>don't actually support C45? You have this endless loop:
There is controller which don't support C45. I will add check for that usin=
g is_c45.
>
>+       /* wait for end of transfer */
>+       while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
>+               cpu_relax();
>
>If there is hardware which does not support C45, will this loop forever?
>
>	Andrew
Yes, this bit is supposed to be set. I will add timeout here.

Regards,
Parshuram Thombare