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[209.132.180.67]) by mx.google.com with ESMTP id i12si11020982pgq.466.2019.02.26.02.29.04; Tue, 26 Feb 2019 02:29:19 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728056AbfBZK0v (ORCPT + 99 others); Tue, 26 Feb 2019 05:26:51 -0500 Received: from baldur.buserror.net ([165.227.176.147]:58482 "EHLO baldur.buserror.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725977AbfBZK0u (ORCPT ); Tue, 26 Feb 2019 05:26:50 -0500 X-Greylist: delayed 2351 seconds by postgrey-1.27 at vger.kernel.org; Tue, 26 Feb 2019 05:26:49 EST Received: from [2601:449:8400:7293:12bf:48ff:fe84:c9a0] by baldur.buserror.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1gyZIX-0005qT-C1; Tue, 26 Feb 2019 03:45:13 -0600 Message-ID: <07441256501ad8bd45b187cf6e25338b028bc9ac.camel@buserror.net> From: Scott Wood To: Vabhav Sharma , "sudeep.holla@arm.com" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "linuxppc-dev@lists.ozlabs.org" , "linux-arm-kernel@lists.infradead.org" , "mturquette@baylibre.com" , "sboyd@kernel.org" , "rjw@rjwysocki.net" , "viresh.kumar@linaro.org" , "linux-clk@vger.kernel.org" , "linux-pm@vger.kernel.org" , "linux-kernel-owner@vger.kernel.org" , "catalin.marinas@arm.com" , "will.deacon@arm.com" , "gregkh@linuxfoundation.org" , "arnd@arndb.de" , "kstewart@linuxfoundation.org" , "yamada.masahiro@socionext.com" , Leo Li , "shawnguo@kernel.org" Cc: "linux@armlinux.org.uk" , "adrian.hunter@intel.com" , "ulf.hansson@linaro.org" , Yogesh Narayan Gaur , Andy Tang Date: Tue, 26 Feb 2019 03:45:11 -0600 In-Reply-To: <1551126463-5341-5-git-send-email-vabhav.sharma@nxp.com> References: <1551126463-5341-1-git-send-email-vabhav.sharma@nxp.com> <1551126463-5341-5-git-send-email-vabhav.sharma@nxp.com> Organization: Red Hat Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-SA-Exim-Connect-IP: 2601:449:8400:7293:12bf:48ff:fe84:c9a0 X-SA-Exim-Rcpt-To: vabhav.sharma@nxp.com, sudeep.holla@arm.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, mturquette@baylibre.com, sboyd@kernel.org, rjw@rjwysocki.net, viresh.kumar@linaro.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel-owner@vger.kernel.org, catalin.marinas@arm.com, will.deacon@arm.com, gregkh@linuxfoundation.org, arnd@arndb.de, kstewart@linuxfoundation.org, yamada.masahiro@socionext.com, leoyang.li@nxp.com, shawnguo@kernel.org, linux@armlinux.org.uk, adrian.hunter@intel.com, ulf.hansson@linaro.org, yogeshnarayan.gaur@nxp.com, andy.tang@nxp.com X-SA-Exim-Mail-From: oss@buserror.net X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on baldur.localdomain X-Spam-Level: X-Spam-Status: No, score=-16.0 required=5.0 tests=ALL_TRUSTED,BAYES_00 autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Report: * -1.0 ALL_TRUSTED Passed through trusted hosts only via SMTP * -15 BAYES_00 BODY: Bayes spam probability is 0 to 1% * [score: 0.0000] Subject: Re: [PATCH 4/4] clk: qoriq: Add clockgen support for lx2160a X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on baldur.buserror.net) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 2019-02-26 at 08:34 +0000, Vabhav Sharma wrote: > @@ -1435,6 +1446,7 @@ CLK_OF_DECLARE(qoriq_clockgen_t1023, "fsl,t1023- > clockgen", clockgen_init); > CLK_OF_DECLARE(qoriq_clockgen_t1040, "fsl,t1040-clockgen", clockgen_init); > CLK_OF_DECLARE(qoriq_clockgen_t2080, "fsl,t2080-clockgen", clockgen_init); > CLK_OF_DECLARE(qoriq_clockgen_t4240, "fsl,t4240-clockgen", clockgen_init); > +CLK_OF_DECLARE(qoriq_clockgen_lx2160a, "fsl,lx2160a-clockgen", > clockgen_init); The chips were previously in alphabetical order... -Scott