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Tue, 26 Feb 2019 07:05:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=0mdZRh56SUQBbcbH6/ETtMeZJK7aaUw0yL1J2lBHKv0=; b=oicS19GHKT7JtfACreYHo++FTo9xv7Me+uTVEriFTSyJhRIpksmUl5ECSIPPfmzIiAsBbZiz84rlePaNF22bv+BEDh+2nJrGGc4U7YuDlSwcNDcqVycgPMcNDAWs2BEEbl77dIDy9xlQMyEk6R4Hng9HIZvp3X0IG1t7MD6QuTI= Received: from VI1PR04MB4222.eurprd04.prod.outlook.com (52.134.31.21) by VI1PR04MB5101.eurprd04.prod.outlook.com (20.177.50.150) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1643.14; Tue, 26 Feb 2019 12:04:53 +0000 Received: from VI1PR04MB4222.eurprd04.prod.outlook.com ([fe80::b1cb:82a5:aacb:238d]) by VI1PR04MB4222.eurprd04.prod.outlook.com ([fe80::b1cb:82a5:aacb:238d%6]) with mapi id 15.20.1643.019; Tue, 26 Feb 2019 12:04:53 +0000 From: Aisheng Dong To: Anson Huang , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "kernel@pengutronix.de" , "festevam@gmail.com" , "ulf.hansson@linaro.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" CC: dl-linux-imx Subject: RE: [PATCH V4 2/2] dt-bindings: imx: add new resources to scu resource table Thread-Topic: [PATCH V4 2/2] dt-bindings: imx: add new resources to scu resource table Thread-Index: AQHUyyaeCJ4QOUOebEWEXoq3nWLbxaXyAEXQ Date: Tue, 26 Feb 2019 12:04:53 +0000 Message-ID: References: <1550891655-29043-1-git-send-email-Anson.Huang@nxp.com> <1550891655-29043-2-git-send-email-Anson.Huang@nxp.com> In-Reply-To: <1550891655-29043-2-git-send-email-Anson.Huang@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=aisheng.dong@nxp.com; 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received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: FJdNaFNhAVd645/FBKR2OLEQiL2rTg1QwdbxHpE3s7BNuW7/6DCRhwUynIZ8YZKt1yA8zeaBH8JZxT5jWJbnvO6QdSaL1nE5k8H4ZQ1YtrcFXLPMqg0Q9wuaJrc1clWRLmBmHWo7nb40bUk21Md1bL+ilk6x7n5RDm2DElQQAC97YfC7FA2VlyUMdAcTgCrEI9oqy8SYTfC3C9vWdDK2e/KT04vl1ZLEAQAIG+CvG4T8M/2p1bfw22vfP7ccRwzVjrET4hJgYHUFd+KiPQdKQkzS+2cPs0xSZtVKRz7GWASYWn+bExMdt6iU59dJAqYJfM2gRjLWJj8K/kE+gntMjgnYuJ+wHBaegtSp9H9jHE56sk6VqaKsBklUoJTJS+HA0ltWksCdvmML7cwxEF9da0dOl+AeFHgLHk30S2SOmrs= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1bb578bf-84bf-4594-85c9-08d69be29e42 X-MS-Exchange-CrossTenant-originalarrivaltime: 26 Feb 2019 12:04:53.7646 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB5101 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > From: Anson Huang > Sent: Saturday, February 23, 2019 11:20 AM >=20 > Add new resources as below according to latest system controller firmware= for > new features: >=20 > IMX_SC_R_PERF > IMX_SC_R_OCRAM > IMX_SC_R_DMA_5_CH0 > IMX_SC_R_DMA_5_CH1 > IMX_SC_R_DMA_5_CH2 > IMX_SC_R_DMA_5_CH3 > IMX_SC_R_ATTESTATION >=20 > Signed-off-by: Anson Huang > Reviewed-by: Rob Herring Please update the patch title to: dt-bindings: firmware: imx-scu: xxxx Otherwise: Reviewed-by: Dong Aisheng Regards Dong Aisheng > --- > No changes since V3. > --- > include/dt-bindings/firmware/imx/rsrc.h | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) >=20 > diff --git a/include/dt-bindings/firmware/imx/rsrc.h > b/include/dt-bindings/firmware/imx/rsrc.h > index d69f934..4e61f64 100644 > --- a/include/dt-bindings/firmware/imx/rsrc.h > +++ b/include/dt-bindings/firmware/imx/rsrc.h > @@ -36,6 +36,7 @@ > #define IMX_SC_R_DC_0_BLIT1 20 > #define IMX_SC_R_DC_0_BLIT2 21 > #define IMX_SC_R_DC_0_BLIT_OUT 22 > +#define IMX_SC_R_PERF 23 > #define IMX_SC_R_DC_0_WARP 25 > #define IMX_SC_R_DC_0_VIDEO0 28 > #define IMX_SC_R_DC_0_VIDEO1 29 > @@ -322,7 +323,7 @@ > #define IMX_SC_R_IRQSTR_SCU2 321 > #define IMX_SC_R_IRQSTR_DSP 322 > #define IMX_SC_R_ELCDIF_PLL 323 > -#define IMX_SC_R_UNUSED6 324 > +#define IMX_SC_R_OCRAM 324 > #define IMX_SC_R_AUDIO_PLL_0 325 > #define IMX_SC_R_PI_0 326 > #define IMX_SC_R_PI_0_PWM_0 327 > @@ -539,6 +540,11 @@ > #define IMX_SC_R_VPU_MU_3 538 > #define IMX_SC_R_VPU_ENC_1 539 > #define IMX_SC_R_VPU 540 > -#define IMX_SC_R_LAST 541 > +#define IMX_SC_R_DMA_5_CH0 541 > +#define IMX_SC_R_DMA_5_CH1 542 > +#define IMX_SC_R_DMA_5_CH2 543 > +#define IMX_SC_R_DMA_5_CH3 544 > +#define IMX_SC_R_ATTESTATION 545 > +#define IMX_SC_R_LAST 546 >=20 > #endif /* __DT_BINDINGS_RSCRC_IMX_H */ > -- > 2.7.4