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From:   "Ghannam, Yazen" <Yazen.Ghannam@amd.com>
To:     "linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>
CC:     "Ghannam, Yazen" <Yazen.Ghannam@amd.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "bp@alien8.de" <bp@alien8.de>
Subject: [PATCH v2 4/6] EDAC/amd64: Recognize x16 Symbol Size
Thread-Topic: [PATCH v2 4/6] EDAC/amd64: Recognize x16 Symbol Size
Thread-Index: AQHUzfhPcmfYqU2pLEWh5oRAOe0cLw==
Date:   Tue, 26 Feb 2019 17:25:47 +0000
Message-ID: <20190226172532.12924-4-Yazen.Ghannam@amd.com>
References: <20190226172532.12924-1-Yazen.Ghannam@amd.com>
In-Reply-To: <20190226172532.12924-1-Yazen.Ghannam@amd.com>
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From: Yazen Ghannam <yazen.ghannam@amd.com>

Future AMD systems may support x16 symbol sizes.

Recognize if a system is using x16 symbol size. Also, simplify the print
statement.

Note that a x16 syndrome vector table is not necessary like with x4 or
x8. This is because systems that support x16 symbol sizes will be SMCA
systems. In which case, the syndrome can be directly extracted from the
MCA_SYND[Syndrome] field.

Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
Link:
https://lkml.kernel.org/r/20190219202536.15462-3-Yazen.Ghannam@amd.com

v1->v2:
* Apply Boris' fixup.

 drivers/edac/amd64_edac.c | 21 ++++++++++-----------
 drivers/edac/amd64_edac.h |  2 +-
 2 files changed, 11 insertions(+), 12 deletions(-)

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index c82aafb7246a..810345572808 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -897,8 +897,7 @@ static void dump_misc_regs(struct amd64_pvt *pvt)
=20
 	edac_dbg(1, "  DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no");
=20
-	amd64_info("using %s syndromes.\n",
-			((pvt->ecc_sym_sz =3D=3D 8) ? "x8" : "x4"));
+	amd64_info("using x%u syndromes.\n", pvt->ecc_sym_sz);
 }
=20
 /*
@@ -2609,17 +2608,17 @@ static void determine_ecc_sym_sz(struct amd64_pvt *=
pvt)
=20
 		for_each_umc(i) {
 			/* Check enabled channels only: */
-			if ((pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) &&
-			    (pvt->umc[i].ecc_ctrl & BIT(7))) {
-				pvt->ecc_sym_sz =3D 8;
-				break;
+			if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) {
+				if (pvt->umc[i].ecc_ctrl & BIT(9)) {
+					pvt->ecc_sym_sz =3D 16;
+					return;
+				} else if (pvt->umc[i].ecc_ctrl & BIT(7)) {
+					pvt->ecc_sym_sz =3D 8;
+					return;
+				}
 			}
 		}
-
-		return;
-	}
-
-	if (pvt->fam >=3D 0x10) {
+	} else if (pvt->fam >=3D 0x10) {
 		u32 tmp;
=20
 		amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp);
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index 40e63cea2d81..44d81eccfe0a 100644
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -370,7 +370,7 @@ struct amd64_pvt {
 	u32 dct_sel_hi;		/* DRAM Controller Select High */
 	u32 online_spare;	/* On-Line spare Reg */
=20
-	/* x4 or x8 syndromes in use */
+	/* x4, x8, or x16 syndromes in use */
 	u8 ecc_sym_sz;
=20
 	/* place to store error injection parameters prior to issue */
--=20
2.17.1