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Tue, 26 Feb 2019 20:28:34 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=DrHTnIpqOsWp1sorKavNCaDKeym4sGa7ZutNrdbv8Oo=; b=Kkic222PWWYbewG/W2+x6ajarCTCMnXWlzeVE/YUhWvRQrqWEPK7dmOAiz6zAjohEkR1cupG9WHtJDSnUR8gXoyWDpWHFfG3Dq1LfTeYcQDJd31UZpMBf24Mv7hw7R1/Bemn+EUgDyvw9M4S6f+DC6EA+YIqAO/6bKwNLkvGblc= Received: from DB3PR0402MB3916.eurprd04.prod.outlook.com (52.134.72.18) by DB3PR0402MB3772.eurprd04.prod.outlook.com (52.134.71.19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1643.18; Wed, 27 Feb 2019 01:28:27 +0000 Received: from DB3PR0402MB3916.eurprd04.prod.outlook.com ([fe80::1cb4:3e1c:fc85:7ed7]) by DB3PR0402MB3916.eurprd04.prod.outlook.com ([fe80::1cb4:3e1c:fc85:7ed7%2]) with mapi id 15.20.1643.019; Wed, 27 Feb 2019 01:28:26 +0000 From: Anson Huang To: "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "kernel@pengutronix.de" , Fabio Estevam , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "mturquette@baylibre.com" , "sboyd@kernel.org" , Abel Vesa , "l.stach@pengutronix.de" , "agx@sigxcpu.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-clk@vger.kernel.org" CC: dl-linux-imx Subject: [PATCH RESEND V2 1/2] clk: imx8mq: add GPIO clocks to clock tree Thread-Topic: [PATCH RESEND V2 1/2] clk: imx8mq: add GPIO clocks to clock tree Thread-Index: AQHUzju83XkEqBBPo0W2mhbzy8FScA== Date: Wed, 27 Feb 2019 01:28:26 +0000 Message-ID: <1551230622-30660-1-git-send-email-Anson.Huang@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK0PR04CA0022.apcprd04.prod.outlook.com (2603:1096:203:36::34) To DB3PR0402MB3916.eurprd04.prod.outlook.com (2603:10a6:8:10::18) x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.66] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 8bec0cde-b41e-49b2-7e68-08d69c52df44 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600127)(711020)(4605104)(4618075)(2017052603328)(7153060)(7193020);SRVR:DB3PR0402MB3772; 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received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) authentication-results: spf=none (sender IP is ) smtp.mailfrom=anson.huang@nxp.com; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: x4TWHMeNuSTc6k4yq374iZgJvNB/IsKXPev3thVdLs+utvAD5dvu9Prw8pRw0l3hXLA9z8Fpj7fL8MM5x3XflcFWrHkFwGddqHo79Is6XvaSxuaXs4j7tx04urXs0sRLhCrFVGbuMSfNI7zM+4hec37qLS0nVcYQJoFzvEO7hnlrpNlwWmubNlVPyqRi1xJWlGx+0DMs7Iinfc/8dYAxbHzLqKSpS2GAV+w3icWUocLqsjAgxoluZxtGWp7ngTcVyIyDqONr6+GlVSXaSk5RVfBev0DalwS0gqWndsDkE8k9VDhXTvUohG1w52Q+pVjdz6bF3BMmnBS98H/g5GkZeGIYhadrOt/vGaYI2SYN+DNN/XLXE+G9pQtaAjmt6xQA7PkSatIVFlhGZ5h7HnZuoqIOO5bLG2MAyPD+Ef6LHaA= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8bec0cde-b41e-49b2-7e68-08d69c52df44 X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Feb 2019 01:28:21.7898 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0402MB3772 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org i.MX8MQ has clock gate for each GPIO bank, add them into clock tree for GPIO driver to manage. Signed-off-by: Anson Huang --- No changes, just rebase to clk-next. --- drivers/clk/imx/clk-imx8mq.c | 5 +++++ include/dt-bindings/clock/imx8mq-clock.h | 8 +++++++- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c index 01c771f..789dc8e 100644 --- a/drivers/clk/imx/clk-imx8mq.c +++ b/drivers/clk/imx/clk-imx8mq.c @@ -510,6 +510,11 @@ static int imx8mq_clocks_probe(struct platform_device = *pdev) clks[IMX8MQ_CLK_ECSPI2_ROOT] =3D imx_clk_gate4("ecspi2_root_clk", "ecspi2= ", base + 0x4080, 0); clks[IMX8MQ_CLK_ECSPI3_ROOT] =3D imx_clk_gate4("ecspi3_root_clk", "ecspi3= ", base + 0x4090, 0); clks[IMX8MQ_CLK_ENET1_ROOT] =3D imx_clk_gate4("enet1_root_clk", "enet_axi= ", base + 0x40a0, 0); + clks[IMX8MQ_CLK_GPIO1_ROOT] =3D imx_clk_gate4("gpio1_root_clk", "ipg_root= ", base + 0x40b0, 0); + clks[IMX8MQ_CLK_GPIO2_ROOT] =3D imx_clk_gate4("gpio2_root_clk", "ipg_root= ", base + 0x40c0, 0); + clks[IMX8MQ_CLK_GPIO3_ROOT] =3D imx_clk_gate4("gpio3_root_clk", "ipg_root= ", base + 0x40d0, 0); + clks[IMX8MQ_CLK_GPIO4_ROOT] =3D imx_clk_gate4("gpio4_root_clk", "ipg_root= ", base + 0x40e0, 0); + clks[IMX8MQ_CLK_GPIO5_ROOT] =3D imx_clk_gate4("gpio5_root_clk", "ipg_root= ", base + 0x40f0, 0); clks[IMX8MQ_CLK_GPT1_ROOT] =3D imx_clk_gate4("gpt1_root_clk", "gpt1", bas= e + 0x4100, 0); clks[IMX8MQ_CLK_I2C1_ROOT] =3D imx_clk_gate4("i2c1_root_clk", "i2c1", bas= e + 0x4170, 0); clks[IMX8MQ_CLK_I2C2_ROOT] =3D imx_clk_gate4("i2c2_root_clk", "i2c2", bas= e + 0x4180, 0); diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings= /clock/imx8mq-clock.h index 491e39c..b58cc64 100644 --- a/include/dt-bindings/clock/imx8mq-clock.h +++ b/include/dt-bindings/clock/imx8mq-clock.h @@ -394,5 +394,11 @@ #define IMX8MQ_CLK_CLKO1 268 #define IMX8MQ_CLK_ARM 269 =20 -#define IMX8MQ_CLK_END 270 +#define IMX8MQ_CLK_GPIO1_ROOT 270 +#define IMX8MQ_CLK_GPIO2_ROOT 271 +#define IMX8MQ_CLK_GPIO3_ROOT 272 +#define IMX8MQ_CLK_GPIO4_ROOT 273 +#define IMX8MQ_CLK_GPIO5_ROOT 274 + +#define IMX8MQ_CLK_END 275 #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */ --=20 2.7.4