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[209.132.180.67]) by mx.google.com with ESMTP id w5si13895278pgr.93.2019.02.28.07.03.06; Thu, 28 Feb 2019 07:03:22 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733034AbfB1O0q (ORCPT + 99 others); Thu, 28 Feb 2019 09:26:46 -0500 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:51024 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731073AbfB1O0P (ORCPT ); Thu, 28 Feb 2019 09:26:15 -0500 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x1SEGHPc022515; Thu, 28 Feb 2019 15:26:02 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2qtvh3we8j-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 28 Feb 2019 15:26:02 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id E43C938; Thu, 28 Feb 2019 14:26:01 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas24.st.com [10.75.90.94]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id CDDBE5993; Thu, 28 Feb 2019 14:26:01 +0000 (GMT) Received: from SAFEX1HUBCAS22.st.com (10.75.90.93) by Safex1hubcas24.st.com (10.75.90.94) with Microsoft SMTP Server (TLS) id 14.3.361.1; Thu, 28 Feb 2019 15:26:01 +0100 Received: from localhost (10.201.23.19) by Webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Thu, 28 Feb 2019 15:26:01 +0100 From: Hugues Fruchet To: Alexandre Torgue , Rob Herring , Mark Rutland CC: , , , Subject: [PATCH 3/4] ARM: dts: stm32: add DCMI pins to stm32mp157c Date: Thu, 28 Feb 2019 15:25:44 +0100 Message-ID: <1551363945-19497-4-git-send-email-hugues.fruchet@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1551363945-19497-1-git-send-email-hugues.fruchet@st.com> References: <1551363945-19497-1-git-send-email-hugues.fruchet@st.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.201.23.19] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-02-28_07:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add DCMI pins to stm32mp157c. Signed-off-by: Hugues Fruchet --- arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 41 +++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi index 6b3a9c6..b299afc 100644 --- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi @@ -414,6 +414,47 @@ bias-disable; }; }; + + dcmi_pins_a: dcmi-0 { + pins { + pinmux = ,/* DCMI_HSYNC */ + ,/* DCMI_VSYNC */ + ,/* DCMI_PIXCLK */ + ,/* DCMI_D0 */ + ,/* DCMI_D1 */ + ,/* DCMI_D2 */ + ,/* DCMI_D3 */ + ,/* DCMI_D4 */ + ,/* DCMI_D5 */ + ,/* DCMI_D6 */ + ,/* DCMI_D7 */ + ,/* DCMI_D8 */ + ,/* DCMI_D9 */ + ,/* DCMI_D10 */ + ;/* DCMI_D11 */ + bias-disable; + }; + }; + + dcmi_sleep_pins_a: dcmi-sleep-0 { + pins { + pinmux = ,/* DCMI_HSYNC */ + ,/* DCMI_VSYNC */ + ,/* DCMI_PIXCLK */ + ,/* DCMI_D0 */ + ,/* DCMI_D1 */ + ,/* DCMI_D2 */ + ,/* DCMI_D3 */ + ,/* DCMI_D4 */ + ,/* DCMI_D5 */ + ,/* DCMI_D6 */ + ,/* DCMI_D7 */ + ,/* DCMI_D8 */ + ,/* DCMI_D9 */ + ,/* DCMI_D10 */ + ;/* DCMI_D11 */ + }; + }; }; pinctrl_z: pin-controller-z@54004000 { -- 2.7.4