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From:   "Ghannam, Yazen" <Yazen.Ghannam@amd.com>
To:     "linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>
CC:     "Ghannam, Yazen" <Yazen.Ghannam@amd.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "bp@alien8.de" <bp@alien8.de>
Subject: [PATCH v3 3/6] EDAC/amd64: Support more than two Unified Memory
 Controllers
Thread-Topic: [PATCH v3 3/6] EDAC/amd64: Support more than two Unified Memory
 Controllers
Thread-Index: AQHUz3tUScjw79nRdk2YLwwHsenigQ==
Date:   Thu, 28 Feb 2019 15:36:10 +0000
Message-ID: <20190228153558.127292-3-Yazen.Ghannam@amd.com>
References: <20190228153558.127292-1-Yazen.Ghannam@amd.com>
In-Reply-To: <20190228153558.127292-1-Yazen.Ghannam@amd.com>
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From: Yazen Ghannam <yazen.ghannam@amd.com>

The first few models of Family 17h all had 2 Unified Memory Controllers
per Die, so this was treated as a fixed value. However, future systems
may have more Unified Memory Controllers per Die.

Related to this, the channel number and base address of a Unified Memory
Controller were found by matching on fixed, known values. However,
current and future systems follow this pattern for the channel number
and base address of a Unified Memory Controller: 0xYXXXXX, where Y is
the channel number. So matching on hardcoded values is not necessary.

Set the number of Unified Memory Controllers at driver init time based
on the Family/Model. Also, update the functions that find the channel
number and base address of a Unified Memory Controller to support more
than two.

Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
Link:
https://lkml.kernel.org/r/20190226172532.12924-2-Yazen.Ghannam@amd.com

v2->v3:
* Apply V2 Patch 3 before V2 Patch 2.

v1->v2:
* Fix tone in commit message.
* Clarify pattern used for finding channel numbers.
* Remove macro for looping over number of UMCs.
* Move function to find number of UMCs to single driver init function.
* Rename function that finds the number of UMCs.
* Add comments for new variables and functions.
* Move function to find number of UMCs out of header.

 drivers/edac/amd64_edac.c | 44 ++++++++++++++++++++++++---------------
 drivers/edac/amd64_edac.h | 10 ++++++---
 2 files changed, 34 insertions(+), 20 deletions(-)

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index e4fd459d807a..25416c608908 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -450,7 +450,7 @@ static void get_cs_base_and_mask(struct amd64_pvt *pvt,=
 int csrow, u8 dct,
 	for (i =3D 0; i < pvt->csels[dct].m_cnt; i++)
=20
 #define for_each_umc(i) \
-	for (i =3D 0; i < NUM_UMCS; i++)
+	for (i =3D 0; i < num_umcs; i++)
=20
 /*
  * @input_addr is an InputAddr associated with the node given by mci. Retu=
rn the
@@ -2476,18 +2476,14 @@ static inline void decode_bus_error(int node_id, st=
ruct mce *m)
  * To find the UMC channel represented by this bank we need to match on it=
s
  * instance_id. The instance_id of a bank is held in the lower 32 bits of =
its
  * IPID.
+ *
+ * Currently, we can derive the channel number by looking at the 6th nibbl=
e in
+ * the instance_id. For example, instance_id=3D0xYXXXXX where Y is the cha=
nnel
+ * number.
  */
-static int find_umc_channel(struct amd64_pvt *pvt, struct mce *m)
+static int find_umc_channel(struct mce *m)
 {
-	u32 umc_instance_id[] =3D {0x50f00, 0x150f00};
-	u32 instance_id =3D m->ipid & GENMASK(31, 0);
-	int i, channel =3D -1;
-
-	for (i =3D 0; i < ARRAY_SIZE(umc_instance_id); i++)
-		if (umc_instance_id[i] =3D=3D instance_id)
-			channel =3D i;
-
-	return channel;
+	return (m->ipid & GENMASK(31, 0)) >> 20;
 }
=20
 static void decode_umc_error(int node_id, struct mce *m)
@@ -2509,11 +2505,7 @@ static void decode_umc_error(int node_id, struct mce=
 *m)
 	if (m->status & MCI_STATUS_DEFERRED)
 		ecc_type =3D 3;
=20
-	err.channel =3D find_umc_channel(pvt, m);
-	if (err.channel < 0) {
-		err.err_code =3D ERR_CHANNEL;
-		goto log_error;
-	}
+	err.channel =3D find_umc_channel(m);
=20
 	if (umc_normaddr_to_sysaddr(m->addr, pvt->mc_node_id, err.channel, &sys_a=
ddr)) {
 		err.err_code =3D ERR_NORM_ADDR;
@@ -3252,6 +3244,22 @@ static const struct attribute_group *amd64_edac_attr=
_groups[] =3D {
 	NULL
 };
=20
+/* Set the number of Unified Memory Controllers in the system. */
+static void compute_num_umcs(void)
+{
+	u8 model =3D boot_cpu_data.x86_model;
+
+	if (boot_cpu_data.x86 < 0x17)
+		return;
+
+	if (model >=3D 0x30 && model <=3D 0x3f)
+		num_umcs =3D 8;
+	else
+		num_umcs =3D 2;
+
+	edac_dbg(1, "Number of UMCs: %x", num_umcs);
+}
+
 static int init_one_instance(unsigned int nid)
 {
 	struct pci_dev *F3 =3D node_to_amd_nb(nid)->misc;
@@ -3276,7 +3284,7 @@ static int init_one_instance(unsigned int nid)
 		goto err_free;
=20
 	if (pvt->fam >=3D 0x17) {
-		pvt->umc =3D kcalloc(NUM_UMCS, sizeof(struct amd64_umc), GFP_KERNEL);
+		pvt->umc =3D kcalloc(num_umcs, sizeof(struct amd64_umc), GFP_KERNEL);
 		if (!pvt->umc) {
 			ret =3D -ENOMEM;
 			goto err_free;
@@ -3497,6 +3505,8 @@ static int __init amd64_edac_init(void)
 	if (!msrs)
 		goto err_free;
=20
+	compute_num_umcs();
+
 	for (i =3D 0; i < amd_nb_num(); i++) {
 		err =3D probe_one_instance(i);
 		if (err) {
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index de8dbb0b42b5..40e63cea2d81 100644
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -274,7 +274,11 @@
=20
 #define UMC_SDP_INIT			BIT(31)
=20
-#define NUM_UMCS			2
+/*
+ * Number of Unified Memory Controllers
+ * Set during driver init based on family/model.
+ */
+static u8 num_umcs;
=20
 enum amd_families {
 	K8_CPUS =3D 0,
@@ -399,8 +403,8 @@ struct err_info {
=20
 static inline u32 get_umc_base(u8 channel)
 {
-	/* ch0: 0x50000, ch1: 0x150000 */
-	return 0x50000 + (!!channel << 20);
+	/* chY: 0xY50000 */
+	return 0x50000 + (channel << 20);
 }
=20
 static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i)
--=20
2.17.1