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Thu, 28 Feb 2019 20:24:23 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=mbTVdL50FF+r5yKuvVMQtilzKd/gXJTelKO/VTKUpUA=; b=ekiWPMuqeBegbJTXzNdPQLEZ+2X6qd/1FhWvx161eckXT3hgT9tUc8xf4jAHoXR0WxyetO/a45XP1Nz8q4RILPpz5q2i4/Q3D0F4cX1vbVb3s3kiv7DJoY5hiyLLxzvJN4qOtN+9cXO+nGXf90nLdZOBY8GXxIkjseJce9XnBaY= Received: from DB3PR0402MB3916.eurprd04.prod.outlook.com (52.134.72.18) by DB3PR0402MB3756.eurprd04.prod.outlook.com (52.134.73.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1643.21; Fri, 1 Mar 2019 01:24:18 +0000 Received: from DB3PR0402MB3916.eurprd04.prod.outlook.com ([fe80::1cb4:3e1c:fc85:7ed7]) by DB3PR0402MB3916.eurprd04.prod.outlook.com ([fe80::1cb4:3e1c:fc85:7ed7%2]) with mapi id 15.20.1665.015; Fri, 1 Mar 2019 01:24:18 +0000 From: Anson Huang To: "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "kernel@pengutronix.de" , "festevam@gmail.com" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" CC: dl-linux-imx Subject: [PATCH V4 1/3] dt-bindings: memory-controllers: freescale: add MMDC binding doc Thread-Topic: [PATCH V4 1/3] dt-bindings: memory-controllers: freescale: add MMDC binding doc Thread-Index: AQHUz819CWq3wsojT0+oGW04Z701rg== Date: Fri, 1 Mar 2019 01:24:18 +0000 Message-ID: <1551403185-16314-1-git-send-email-Anson.Huang@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK2PR02CA0145.apcprd02.prod.outlook.com (2603:1096:202:16::29) To DB3PR0402MB3916.eurprd04.prod.outlook.com (2603:10a6:8:10::18) authentication-results: spf=none (sender IP is ) smtp.mailfrom=anson.huang@nxp.com; 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received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: 3r25SUXV6+POExA4ABVylboN4NgshpthrZ5Q1QUqvtrSrWZsgi8mtHG6cBuELT3VrosZRrZ16JDMt4IMNnvAKX883PwZXMdsloBrs1SL71itMPhMKxQI6afRGOCRAPlS2IMPMcz8zUpOI3AtDjgVjiXlGvtbGnuqnbdfLBjBKVdZV3/SLqbA2gJnxfiUpqWIckZ2Oj7Ii6JkldSWpgzRs1iXEuJQHud6Um0w6Ol5Akzhl2KHwiIrcKLuUvDRC5ymFK7lK9zkLip3fc4iU+TedgSfsEBCmkI3s5/OempMBIVMyjhVJzveYgg5Y0nc3HRDYhVrQ23tpJcs5JGRF0R0LIES9UfmouFuSS+j3LPf4flRB7eZnnuW6uYeouYVK4BSNtvacGyzXB9C74Ep8+lCaujaVakfO5MCh+oLjkoBumk= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: d4fa7521-2a8b-4a1a-554f-08d69de49fd0 X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Mar 2019 01:24:18.3962 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0402MB3756 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Freescale MMDC (Multi Mode DDR Controller) driver is supported since i.MX6Q, but not yet documented, this patch adds binding doc for MMDC module driver. Signed-off-by: Anson Huang --- Changes since V3: - add i.MX6QP compatible name. --- .../bindings/memory-controllers/fsl/mmdc.txt | 33 ++++++++++++++++++= ++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/fs= l/mmdc.txt diff --git a/Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.= txt b/Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.txt new file mode 100644 index 0000000..e4e0b50 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.txt @@ -0,0 +1,33 @@ +Freescale Multi Mode DDR controller (MMDC) + +Required properties : +- compatible : should be one of following: + for i.MX6Q/i.MX6DL: + - "fsl,imx6q-mmdc"; + for i.MX6QP: + - "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc"; + for i.MX6SL: + - "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc"; + for i.MX6SLL: + - "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc"; + for i.MX6SX: + - "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc"; + for i.MX6UL/i.MX6ULL/i.MX6ULZ: + - "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc"; + for i.MX7ULP: + - "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc"; +- reg : address and size of MMDC DDR controller registers + +Optional properties : +- clocks : the clock provided by the SoC to access the MMDC registers + +Example : + mmdc0: memory-controller@21b0000 { /* MMDC0 */ + compatible =3D "fsl,imx6q-mmdc"; + reg =3D <0x021b0000 0x4000>; + clocks =3D <&clks IMX6QDL_CLK_MMDC_P0_IPG>; + }; + + mmdc1: memory-controller@21b4000 { /* MMDC1 */ + reg =3D <0x021b4000 0x4000>; + }; --=20 2.7.4