Received: by 2002:ac0:aed5:0:0:0:0:0 with SMTP id t21csp909659imb; Fri, 1 Mar 2019 18:54:00 -0800 (PST) X-Google-Smtp-Source: AHgI3IY01xiQa+PtVaOm0xlcvgeaCosrzXEtsugzNq3HcldpfFg5+X+Ez5fBSsj3pKrsYLJgb7Nu X-Received: by 2002:aa7:87c6:: with SMTP id i6mr8821515pfo.208.1551495240087; Fri, 01 Mar 2019 18:54:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551495240; cv=none; d=google.com; s=arc-20160816; b=S+HbSYhYZR9003HDSo32gQWB3NTymPmxqxMVCCd93h9oi7WnQk0xiXEBldx2dIG4mN o6Xb/vB9/6G3em7yDRqYFkfPJ6NhiyRHTIA3YGnZx5eKdw/3P7fPJ9Xs+i2p4FK9N31B OTkAx8lJjUEI40RV8J7w03yDqs6hjpCHWynrH6bOfEznKpzw53uXroC6nUY4Nl59PUuF SQxyKJLq0MwhkcEoE32a+oFJt0AZvecghZVu3hF9SQNl4FOh6tf3Y9U6nIVz2uzZe8L2 4C0Aqd9i6gTf3OpdcDEBbhVKqcal3/sHsRXOIBD8Jrz8ICMFyBL5p/RFoBK76oUg1Qwq +jTg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=VylRtWz/Wjd3kFv/jmP9W/lrljavVU6iK5fk7EDkfIY=; b=MyjkwLrcq3OYPCagxZrso+ZjS024mO5w/vYEm/VfBnc+TjbYOGK6JnGclngX/Q719v t51ubfyy6LHPAQTFWYtwJwpdVQvUsR9O88YHlz52+PH0plm0wJ7pIrS2K0XjJea8/uHP /S8vBl5KC+AryKGVpXvCY4Jaow8zIuOms4CbihWNHPPDAxHInL5tCh/XjGxhl3FyT0fn 4K25Oir+6/c5cryuHVlTo1UiX+OJiRR7WeYf5KgZmZp/O6TD17z4ZFUhruic98XHo6pN C7BRERdnm/Ew/KzNCBeEDHrtkWZ7YS95j0RRq/R6jDJ8i7t0U8odmiG2Y+mXzdh2dPMm MCOQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j27si22322565pgm.305.2019.03.01.18.53.30; Fri, 01 Mar 2019 18:54:00 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727875AbfCBCwc (ORCPT + 99 others); Fri, 1 Mar 2019 21:52:32 -0500 Received: from mga04.intel.com ([192.55.52.120]:49771 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727824AbfCBCwa (ORCPT ); Fri, 1 Mar 2019 21:52:30 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Mar 2019 18:52:28 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,430,1544515200"; d="scan'208";a="148572604" Received: from romley-ivt3.sc.intel.com ([172.25.110.60]) by fmsmga004.fm.intel.com with ESMTP; 01 Mar 2019 18:52:28 -0800 From: Fenghua Yu To: "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "H Peter Anvin" , "Paolo Bonzini" , "Dave Hansen" , "Ashok Raj" , "Peter Zijlstra" , "Ravi V Shankar" , "Xiaoyao Li " Cc: "linux-kernel" , "x86" , kvm@vger.kernel.org, Fenghua Yu Subject: [PATCH v4 06/17] x86/msr-index: Define IA32_CORE_CAPABILITY MSR and #AC exception for split lock bit Date: Fri, 1 Mar 2019 18:45:00 -0800 Message-Id: <1551494711-213533-7-git-send-email-fenghua.yu@intel.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1551494711-213533-1-git-send-email-fenghua.yu@intel.com> References: <1551494711-213533-1-git-send-email-fenghua.yu@intel.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org A new IA32_CORE_CAPABILITY MSR (0xCF) is defined. Each bit in the MSR enumerates a model specific feature. Currently bit 5 enumerates #AC exception for split locked accesses. When bit 5 is 1, split locked accesses will generate #AC exception. When bit 5 is 0, split locked accesses will not generate #AC exception. Please check the latest Intel Architecture Instruction Set Extensions and Future Features Programming Reference for more detailed information on the MSR and the split lock bit. Signed-off-by: Fenghua Yu --- arch/x86/include/asm/msr-index.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 8e40c2446fd1..549e73dcca15 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -59,6 +59,9 @@ #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) +#define MSR_IA32_CORE_CAPABILITY 0x000000cf +#define CORE_CAP_SPLIT_LOCK_DETECT BIT(5) /* Detect split lock */ + #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 #define NHM_C3_AUTO_DEMOTE (1UL << 25) #define NHM_C1_AUTO_DEMOTE (1UL << 26) -- 2.7.4