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[209.85.167.43]) by smtp.gmail.com with ESMTPSA id m10sm1048688lfk.57.2019.03.03.10.55.24 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 03 Mar 2019 10:55:24 -0800 (PST) Received: by mail-lf1-f43.google.com with SMTP id v185so1902755lfa.11 for ; Sun, 03 Mar 2019 10:55:24 -0800 (PST) X-Received: by 2002:a19:3f44:: with SMTP id m65mr8007506lfa.136.1551638946307; Sun, 03 Mar 2019 10:49:06 -0800 (PST) MIME-Version: 1.0 References: <20190301140348.25175-1-will.deacon@arm.com> <20190301140348.25175-2-will.deacon@arm.com> <1551575210.6lwpiqtg5k.astroid@bobo.none> <1551583190.duzqnmfnvg.astroid@bobo.none> <1551606848.8cceyn7nhv.astroid@bobo.none> In-Reply-To: <1551606848.8cceyn7nhv.astroid@bobo.none> From: Linus Torvalds Date: Sun, 3 Mar 2019 10:48:50 -0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 01/20] asm-generic/mmiowb: Add generic implementation of mmiowb() tracking To: Nicholas Piggin Cc: Andrea Parri , Arnd Bergmann , Benjamin Herrenschmidt , Rich Felker , David Howells , Daniel Lustig , linux-arch , Linux List Kernel Mailing , "Maciej W. Rozycki" , Ingo Molnar , Michael Ellerman , Palmer Dabbelt , Paul Burton , "Paul E. McKenney" , Peter Zijlstra , Alan Stern , Tony Luck , Will Deacon , Yoshinori Sato Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, Mar 3, 2019 at 2:05 AM Nicholas Piggin wrote: > > Why even bother with it at all, "internal" or not? Just get rid of > mmiowb, the concept is obsolete. It *is* gone, for chrissake! Only the name remains as an internal detail of "this is what we need to do". > Pretend ia64 doesn't exist for a minute. Now the regular mb/wmb barriers > orders IO across CPUs with respect to their cacheable accesses. Stop with the total red herring already. THIS HAS NOTHING TO DO WITH mb()/wmb(). As long as you keep bringing those up, you're only showing that you're talking about the wrong thing. > Regardless of whether that cacheable access is a spin lock, a bit lock, > an atomic, a mutex... This is how it was before mmiowb came along. No. Beflore mmiowb() came along, there was one rule: do what x86 does. And x86 orders mmio inside spinlocks. Seriously. Notice how there's not a single "barrier" mentioned here anywhere in the above. No "mb()", no "wmb()", no nothing. Only "spinlocks order IO". That's the fundamental rule (that we broke for ia64), and all that matters for this patch series. Stop talking about wmb(). It's irrelevant. A spinlock does not *contain* a wmb(). Nobody even _cares_ about wmb(). They are entirely irrelevant wrt IO, because IO is ordered on any particular CPU anyway (which is what wmb() enforces). Only when you do special things like __raw_writel() etc does wmb() matter, but at that point this whole series is entirely irrelevant, and once again, that's still about just ordering on a single CPU. So as long as you talk about wmb(), all you show is that you're talking about something entirely different FROM THIS WHOLE SERIES. And like it or not, ia64 still exists. We support it. It doesn't _matter_ and we don't much care any more, but it still exists. Which is why we have that concept of mmiowb(). On other platforms, mmiowb() might be a wmb(). Or it might not. It might be some other barrier, or it might be a no-op entirely without a barrier at all. It doesn't matter. But mmiowb() exists, and is now happily entirely hidden inside the rule of "spinlocks order MMIO across CPU's". Linus