Received: by 2002:ac0:aed5:0:0:0:0:0 with SMTP id t21csp2069747imb; Sun, 3 Mar 2019 17:01:50 -0800 (PST) X-Google-Smtp-Source: APXvYqyJs+kefHlLgBQn5ae5jLwJf0T6AYveJlEUMa5gRMi3LZ1zO9Z5VQSYiYxljr9mNJWM3rRH X-Received: by 2002:a62:f54d:: with SMTP id n74mr17245329pfh.98.1551661310396; Sun, 03 Mar 2019 17:01:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551661310; cv=none; d=google.com; s=arc-20160816; b=gP8GR7jH5U4kvoG2hZpejqKEgBHPmlrJrGrCvE4AASlEpvqoQvBGDp5eujZdvEYbbF XAFECG4djlooCZJ1lyPmMYkQisxf7TpEO6Qc8zCwifO2u+7gOEI5u5RQgPOwWm6ynEEP 5ZUUGG3/6pVCqemwe7zzJDJqN1c3STzMXK67bGjzU7WHlFdeXQ8dM7y9Wrqke6LqXDg2 DLy4uQyKqJ/6TdJwHmWFxU1+v6OjQbY0J4b4KkLa+ItjCipoisk2FYrVXrzZQljtQWkQ dYw01msEQyoeKhNHPL3Xq3c282utq7+h/BkSH/aoAyCpWOCUMw6D2cCtee7afF1HUM+p SYqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:references :in-reply-to:subject:cc:to:from; bh=bYP80EWYPui4Um0+YIpGH/bXTRvAmx8VYF3OU/sS+Cw=; b=SQMUgFMOE8Tcb8guRPj3s2/+gzYE3aVn+P8NBbVLIeVFZ7tRLyrHimeZccz5Y0pz0s fF0+FTCxuSVkG/jXXdY9gPMVGArXYEL6G07CsY3Z/vLJC4oYOHGCKSfrbzg91NVOrWKW l2+5+36BBx1JwMM4QuHIQVY4ilvvYeJ7n6pe7MYE1FYfvC4Lre4zALsOkK2Os6Q2V/a/ EgvFCoFtWeEybKM954JAsSpVRwLv37f75ClEx2/WXoo6DZBiiRYjbuDMds8lmvf5GoSL V7AWNKFVmE1GIc9FXOPyQyHRSyZupdKQcMx1KwtRiLAPMJMGRaKNsCpswVoxTUkMCE1W x8CQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q202si3977752pgq.194.2019.03.03.17.01.34; Sun, 03 Mar 2019 17:01:50 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726088AbfCDBBP (ORCPT + 99 others); Sun, 3 Mar 2019 20:01:15 -0500 Received: from ozlabs.org ([203.11.71.1]:35733 "EHLO ozlabs.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725995AbfCDBBP (ORCPT ); Sun, 3 Mar 2019 20:01:15 -0500 Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 44CMCn346Pz9s00; Mon, 4 Mar 2019 12:01:09 +1100 (AEDT) From: Michael Ellerman To: Nicholas Piggin , linux-arch@vger.kernel.org, Will Deacon Cc: Andrea Parri , Arnd Bergmann , Benjamin Herrenschmidt , Rich Felker , David Howells , Daniel Lustig , linux-kernel@vger.kernel.org, "Maciej W. Rozycki" , Ingo Molnar , Palmer Dabbelt , Paul Burton , "Paul E. McKenney" , Peter Zijlstra , Alan Stern , Tony Luck , Linus Torvalds , Yoshinori Sato Subject: Re: [PATCH 01/20] asm-generic/mmiowb: Add generic implementation of mmiowb() tracking In-Reply-To: <1551607531.yk1v9azmym.astroid@bobo.none> References: <20190301140348.25175-1-will.deacon@arm.com> <20190301140348.25175-2-will.deacon@arm.com> <1551575210.6lwpiqtg5k.astroid@bobo.none> <87tvgkia0k.fsf@concordia.ellerman.id.au> <1551607531.yk1v9azmym.astroid@bobo.none> Date: Mon, 04 Mar 2019 12:01:08 +1100 Message-ID: <87d0n7bgh7.fsf@concordia.ellerman.id.au> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Nicholas Piggin writes: > Michael Ellerman's on March 3, 2019 7:26 pm: >> Nicholas Piggin writes: ... >>> what was broken about the powerpc one, which is basically: >>> >>> static inline void mmiowb_set_pending(void) >>> { >>> struct mmiowb_state *ms = __mmiowb_state(); >>> ms->mmiowb_pending = 1; >>> } >>> >>> static inline void mmiowb_spin_lock(void) >>> { >>> } >> >> The current powerpc code clears io_sync in spin_lock(). >> >> ie, it would be equivalent to: >> >> static inline void mmiowb_spin_lock(void) >> { >> ms->mmiowb_pending = 0; >> } > > Ah okay that's what I missed. How about we just not do that? Yeah I thought of that too but it's not great. We'd start semi-randomly executing the sync in unlock depending on whether someone had done IO on that CPU prior to the spinlock. eg. writel(x, y); // sets paca->io_sync ... spin_lock(a); ... // No IO in here ... spin_unlock(a); // sync() here because other task did writel(). Which wouldn't be *incorrect*, but would be kind of weird. cheers