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Subject: Re: [PATCH v5 9/9] clk: mediatek: Allow changing PLL rate when it
 is off
From:   James Liao <jamesjj.liao@mediatek.com>
To:     Weiyi Lu <weiyi.lu@mediatek.com>
CC:     Nicolas Boichat <drinkcat@chromium.org>,
        Matthias Brugger <matthias.bgg@gmail.com>,
        Stephen Boyd <sboyd@codeaurora.org>,
        Rob Herring <robh@kernel.org>,
        Fan Chen <fan.chen@mediatek.com>,
        <linux-arm-kernel@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>,
        <linux-mediatek@lists.infradead.org>, <linux-clk@vger.kernel.org>,
        <srv_heupstream@mediatek.com>, <stable@vger.kernel.org>
Date:   Tue, 5 Mar 2019 14:48:09 +0800
In-Reply-To: <20190305050546.23431-11-weiyi.lu@mediatek.com>
References: <20190305050546.23431-1-weiyi.lu@mediatek.com>
         <20190305050546.23431-11-weiyi.lu@mediatek.com>
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On Tue, 2019-03-05 at 13:05 +0800, Weiyi Lu wrote:
> From: James Liao <jamesjj.liao@mediatek.com>
> 
> Some modules may need to change its clock rate before turn on it.
> So changing PLL's rate when it is off should be allowed.
> This patch removes PLL enabled check before set rate, so that
> PLLs can set new frequency even if they are off.
> 
> On MT8173 for example, ARMPLL's enable bit can be controlled by
> other HW. That means ARMPLL may be turned on even if we (CPU / SW)
> set ARMPLL's enable bit as 0. In this case, SW may want and can
> still change ARMPLL's rate by changing its pcw and postdiv settings.
> But without this patch, new pcw setting will not be applied because
> its enable bit is 0.
> 
> Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
> Acked-by: Michael Turquette <mturuqette@baylibre.com>
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>

Reviewed-by: James Liao <jamesjj.liao@mediatek.com>

> ---
>  drivers/clk/mediatek/clk-pll.c | 13 ++-----------
>  1 file changed, 2 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
> index 65cee1d6c400..8d556fc99fed 100644
> --- a/drivers/clk/mediatek/clk-pll.c
> +++ b/drivers/clk/mediatek/clk-pll.c
> @@ -124,9 +124,6 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
>  		int postdiv)
>  {
>  	u32 chg, val;
> -	int pll_en;
> -
> -	pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN;
>  
>  	/* disable tuner */
>  	__mtk_pll_tuner_disable(pll);
> @@ -147,12 +144,7 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
>  			pll->data->pcw_shift);
>  	val |= pcw << pll->data->pcw_shift;
>  	writel(val, pll->pcw_addr);
> -
> -	chg = readl(pll->pcw_chg_addr);
> -
> -	if (pll_en)
> -		chg |= PCW_CHG_MASK;
> -
> +	chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
>  	writel(chg, pll->pcw_chg_addr);
>  	if (pll->tuner_addr)
>  		writel(val + 1, pll->tuner_addr);
> @@ -160,8 +152,7 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
>  	/* restore tuner_en */
>  	__mtk_pll_tuner_enable(pll);
>  
> -	if (pll_en)
> -		udelay(20);
> +	udelay(20);
>  }
>  
>  /*