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[209.132.180.67]) by mx.google.com with ESMTP id b1si1354863pla.382.2019.03.05.00.30.42; Tue, 05 Mar 2019 00:30:57 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727268AbfCEI36 (ORCPT + 99 others); Tue, 5 Mar 2019 03:29:58 -0500 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:31858 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726179AbfCEI34 (ORCPT ); Tue, 5 Mar 2019 03:29:56 -0500 Received: from pps.filterd (m0046037.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x258QPda005139; Tue, 5 Mar 2019 09:29:39 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2qygfxg2st-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 05 Mar 2019 09:29:39 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id A73CA34; Tue, 5 Mar 2019 08:29:38 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas21.st.com [10.75.90.44]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 8A2D71675; Tue, 5 Mar 2019 08:29:38 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.47) by SAFEX1HUBCAS21.st.com (10.75.90.44) with Microsoft SMTP Server (TLS) id 14.3.361.1; Tue, 5 Mar 2019 09:29:38 +0100 Received: from localhost (10.201.23.166) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Tue, 5 Mar 2019 09:29:37 +0100 From: Christophe Roullier To: , , , , , , CC: , , , , , , Subject: [PATCH V3 3/6] dt-bindings: net: stmmac: add phys config properties Date: Tue, 5 Mar 2019 09:29:25 +0100 Message-ID: <1551774568-11732-4-git-send-email-christophe.roullier@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1551774568-11732-1-git-send-email-christophe.roullier@st.com> References: <1551774568-11732-1-git-send-email-christophe.roullier@st.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.201.23.166] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-03-05_04:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add properties to support all Phy config PHY_MODE (MII,GMII, RMII, RGMII) and in normal, PHY wo crystal (25Mhz), PHY wo crystal (50Mhz), No 125Mhz from PHY config. Signed-off-by: Christophe Roullier --- Documentation/devicetree/bindings/net/stm32-dwmac.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.txt b/Documentation/devicetree/bindings/net/stm32-dwmac.txt index 1341012..3524e80 100644 --- a/Documentation/devicetree/bindings/net/stm32-dwmac.txt +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.txt @@ -24,9 +24,9 @@ Required properties: encompases the glue register, and the offset of the control register. Optional properties: -- clock-names: For MPU family "mac-clk-ck" for PHY without quartz -- st,int-phyclk (boolean) : valid only where PHY do not have quartz and need to be clock - by RCC +- clock-names: For MPU family "eth-ck" for PHY without quartz +- st,eth-clk-sel (boolean) : set this property in RGMII PHY when you want to select RCC clock instead of ETH_CLK125. +- st,eth-ref-clk-sel (boolean) : set this property in RMII mode when you have PHY without crystal 50MHz and want to select RCC clock instead of ETH_REF_CLK. Example: -- 2.7.4