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From:   "Ghannam, Yazen" <Yazen.Ghannam@amd.com>
To:     "linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>
CC:     "Ghannam, Yazen" <Yazen.Ghannam@amd.com>,
        Borislav Petkov <bp@suse.de>, Tony Luck <tony.luck@intel.com>,
        "x86@kernel.org" <x86@kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "rafal@milecki.pl" <rafal@milecki.pl>,
        "clemej@gmail.com" <clemej@gmail.com>
Subject: [PATCH 2/2] x86/MCE/AMD, EDAC/mce_amd: Don't report L1 BTB MCA errors
 on some Family 17h models
Thread-Topic: [PATCH 2/2] x86/MCE/AMD, EDAC/mce_amd: Don't report L1 BTB MCA
 errors on some Family 17h models
Thread-Index: AQHU1Sxe2SqGGPluPUqDcNOn3/d2Lg==
Date:   Thu, 7 Mar 2019 21:26:04 +0000
Message-ID: <20190307212552.8865-2-Yazen.Ghannam@amd.com>
References: <20190307212552.8865-1-Yazen.Ghannam@amd.com>
In-Reply-To: <20190307212552.8865-1-Yazen.Ghannam@amd.com>
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From: Yazen Ghannam <yazen.ghannam@amd.com>

AMD Family 17h Models 10h-2Fh may report a high number of L1 BTB MCA
errors under certain conditions. The errors are benign and can safely be
ignored. However, the high error rate may cause the MCA threshold
counter to overflow causing a high rate of thresholding interrupts. In
addition, users may see the errors reported through the AMD MCE decoder
module, even with the interrupt disabled, due to MCA polling.

This error is reported through the Instruction Fetch bank.

Clear the "Counter Present" bit in the Instruction Fetch bank's
MCA_MISC0 register. This will prevent enabling MCA thresholding on this
bank which will prevent the high interrupt rate due to this error.

Filter out this error signature in the AMD MCE decoder module.

Cc: <stable@vger.kernel.org> # 4.14.x: c95b323dcd35: x86/MCE/AMD: Turn off =
MC4_MISC thresholding on all family 0x15 models
Cc: <stable@vger.kernel.org> # 4.14.x: 30aa3d26edb0: x86/MCE/AMD: Carve out=
 the MC4_MISC thresholding quirk
Cc: <stable@vger.kernel.org> # 4.14.x
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
 arch/x86/kernel/cpu/mce/amd.c | 36 +++++++++++++++++++++++------------
 drivers/edac/mce_amd.c        | 21 ++++++++++++++++++++
 2 files changed, 45 insertions(+), 12 deletions(-)

diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c
index 041bb800cda8..810e37df5820 100644
--- a/arch/x86/kernel/cpu/mce/amd.c
+++ b/arch/x86/kernel/cpu/mce/amd.c
@@ -565,21 +565,33 @@ prepare_threshold_block(unsigned int bank, unsigned i=
nt block, u32 addr,
 }
=20
 /*
- * Turn off MC4_MISC thresholding banks on all family 0x15 models since
- * they're not supported there.
+ * Turn off thresholding banks for the following conditions:
+ * - MC4_MISC thresholding is not support on Family 0x15.
+ * - Prevent possible spurious interrupts from the IF bank on Family 0x17
+ *   Models 0x10-0x2F due to Erratum #1114.
  */
-void disable_err_thresholding(struct cpuinfo_x86 *c)
+void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank)
 {
-	int i;
+	int i, num_msrs;
 	u64 hwcr;
 	bool need_toggle;
-	u32 msrs[] =3D {
-		0x00000413, /* MC4_MISC0 */
-		0xc0000408, /* MC4_MISC1 */
-	};
+	u32 msrs[NR_BLOCKS];
+
+	if (c->x86 =3D=3D 0x15 && bank =3D=3D 4) {
+		msrs[0] =3D 0x00000413; /* MC4_MISC0 */
+		msrs[1] =3D 0xc0000408; /* MC4_MISC1 */
+		num_msrs =3D 2;
+	} else if (c->x86 =3D=3D 0x17 &&
+		   (c->x86_model >=3D 0x10 && c->x86_model <=3D 0x2F)) {
+
+		if (smca_get_bank_type(bank) !=3D SMCA_IF)
+			return;
=20
-	if (c->x86 !=3D 0x15)
+		msrs[0] =3D MSR_AMD64_SMCA_MCx_MISC(bank);
+		num_msrs =3D 1;
+	} else {
 		return;
+	}
=20
 	rdmsrl(MSR_K7_HWCR, hwcr);
=20
@@ -590,7 +602,7 @@ void disable_err_thresholding(struct cpuinfo_x86 *c)
 		wrmsrl(MSR_K7_HWCR, hwcr | BIT(18));
=20
 	/* Clear CntP bit safely */
-	for (i =3D 0; i < ARRAY_SIZE(msrs); i++)
+	for (i =3D 0; i < num_msrs; i++)
 		msr_clear_bit(msrs[i], 62);
=20
 	/* restore old settings */
@@ -605,12 +617,12 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
 	unsigned int bank, block, cpu =3D smp_processor_id();
 	int offset =3D -1;
=20
-	disable_err_thresholding(c);
-
 	for (bank =3D 0; bank < mca_cfg.banks; ++bank) {
 		if (mce_flags.smca)
 			smca_configure(bank, cpu);
=20
+		disable_err_thresholding(c, bank);
+
 		for (block =3D 0; block < NR_BLOCKS; ++block) {
 			address =3D get_block_address(address, low, high, bank, block);
 			if (!address)
diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c
index 0a1814dad6cf..4f2bf8ecc513 100644
--- a/drivers/edac/mce_amd.c
+++ b/drivers/edac/mce_amd.c
@@ -1001,6 +1001,24 @@ static inline void amd_decode_err_code(u16 ec)
 	pr_cont("\n");
 }
=20
+static bool smca_filter_mce(struct mce *m)
+{
+	enum smca_bank_types bank_type =3D smca_get_bank_type(m->bank);
+	struct cpuinfo_x86 *c =3D &boot_cpu_data;
+	u8 xec =3D XEC(m->status, xec_mask);
+
+	/*
+	 * Spurious errors of this type may be reported.
+	 * See Family 17h Models 10h-2Fh Erratum #1114.
+	 */
+	if (c->x86 =3D=3D 0x17 &&
+	    (c->x86_model >=3D 0x10 && c->x86_model <=3D 0x2F) &&
+	    bank_type =3D=3D SMCA_IF && xec =3D=3D 10)
+		return true;
+
+	return false;
+}
+
 /*
  * Filter out unwanted MCE signatures here.
  */
@@ -1012,6 +1030,9 @@ static bool amd_filter_mce(struct mce *m)
 	if (m->bank =3D=3D 4 && XEC(m->status, 0x1f) =3D=3D 0x5 && !report_gart_e=
rrors)
 		return true;
=20
+	if (boot_cpu_has(X86_FEATURE_SMCA))
+		return smca_filter_mce(m);
+
 	return false;
 }
=20
--=20
2.17.1