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[209.132.180.67]) by mx.google.com with ESMTP id s61si6673890plb.305.2019.03.08.01.15.46; Fri, 08 Mar 2019 01:16:02 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726456AbfCHJPE (ORCPT + 99 others); Fri, 8 Mar 2019 04:15:04 -0500 Received: from mail-vs1-f67.google.com ([209.85.217.67]:46325 "EHLO mail-vs1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726340AbfCHJPE (ORCPT ); Fri, 8 Mar 2019 04:15:04 -0500 Received: by mail-vs1-f67.google.com with SMTP id b17so4390928vsr.13; Fri, 08 Mar 2019 01:15:03 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=smtJkTEvYhLXfvJ7j6ud+jvOAh89eegxegFHjehZDxE=; b=tvw72b/sQcHwkKj2bEYYP6uxXDs2fOsbE0yNXIO1z/YoWSBblYJI8DVjdy99TzyP8h 9Q954xfdPcAmAQiFoOKcQ83YCX3gwG21BlYjGv+mpyxJI4n95752/Okh8H0hDNeWInGU /8+rOaMmTwhFhvRIm/aJMTSHAQPe8Tpw5Ip/Nv1iZHTAy8tiVejk0mpJEkdl8pGrBA++ CUcSm96wIRFHY8jlfO9+7+jLOd9toVNuYklecqgGSQIjBsi7bwArAHR+1PFeU3M+ex9G dsC4KDvIwLO3UKavryfTbWbFJB7c+iiTc6a0SUF/O/+zwZby8XoTyYdE0wQQ9PJ0bCIu 7rDQ== X-Gm-Message-State: APjAAAXxxpvBI5vAZ/RWXEVnKYT43eSIm/3ImK5ILJUfjutQJpG33qyE DSNX5OWYI6V1Q0ikO/fPomo1hl9iOcaOkYG0CysbPA== X-Received: by 2002:a67:7dd1:: with SMTP id y200mr8326567vsc.96.1552036502736; Fri, 08 Mar 2019 01:15:02 -0800 (PST) MIME-Version: 1.0 References: <1548658158-5460-1-git-send-email-masonccyang@mxic.com.tw> <1548658158-5460-2-git-send-email-masonccyang@mxic.com.tw> <0c54ee2c-016a-bc8e-33ae-fbd04191cc49@cogentembedded.com> In-Reply-To: <0c54ee2c-016a-bc8e-33ae-fbd04191cc49@cogentembedded.com> From: Geert Uytterhoeven Date: Fri, 8 Mar 2019 10:14:51 +0100 Message-ID: Subject: Re: [PATCH v8 1/2] spi: Add Renesas R-Car Gen3 RPC-IF SPI controller driver To: Sergei Shtylyov Cc: Mason Yang , Mark Brown , Marek Vasut , Linux Kernel Mailing List , linux-spi , Boris Brezillon , Linux-Renesas , Geert Uytterhoeven , juliensu@mxic.com.tw, Simon Horman , zhengxunli@mxic.com.tw Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Sergei, On Thu, Mar 7, 2019 at 6:50 PM Sergei Shtylyov wrote: > On 01/28/2019 09:49 AM, Mason Yang wrote: > > Add a driver for Renesas R-Car Gen3 RPC-IF SPI controller. > > > > Signed-off-by: Mason Yang > > Signed-off-by: Sergei Shtylyov > [...] > > diff --git a/drivers/spi/spi-renesas-rpc.c b/drivers/spi/spi-renesas-rpc.c > > new file mode 100644 > > index 0000000..ea12017 > > --- /dev/null > > +++ b/drivers/spi/spi-renesas-rpc.c > > @@ -0,0 +1,804 @@ > [...] > > +static void rpc_spi_hw_init(struct rpc_spi *rpc) > > +{ > > + // > > + // NOTE: The 0x260 are undocumented bits, but they must be set. > > + // RPC_PHYCNT_STRTIM is strobe timing adjustment bit, > > + // 0x0 : the delay is biggest, > > + // 0x1 : the delay is 2nd biggest, > > + // On H3 ES1.x, the value should be 0, while on others, > > + // the value should be 6. > > + // > > + regmap_write(rpc->regmap, RPC_PHYCNT, RPC_PHYCNT_CAL | > > + RPC_PHYCNT_STRTIM(6) | 0x260); > > + > > + // > > + // NOTE: The 0x1511144 are undocumented bits, but they must be set > > + // for RPC_PHYOFFSET1. > > + // The 0x31 are undocumented bits, but they must be set > > + // for RPC_PHYOFFSET2. > > + // > > + regmap_write(rpc->regmap, RPC_PHYOFFSET1, RPC_PHYOFFSET1_DDRTMG(3) | > > + 0x1511144); > > + regmap_write(rpc->regmap, RPC_PHYOFFSET2, 0x31 | > > + RPC_PHYOFFSET2_OCTTMG(4)); > > + regmap_write(rpc->regmap, RPC_SSLDR, RPC_SSLDR_SPNDL(7) | > > + RPC_SSLDR_SLNDL(7) | RPC_SSLDR_SCKDL(7)); > > + regmap_write(rpc->regmap, RPC_CMNCR, RPC_CMNCR_MD | RPC_CMNCR_SFDE | > > + RPC_CMNCR_MOIIO_HIZ | RPC_CMNCR_IOFV_HIZ | > > + RPC_CMNCR_BSZ(0)); > > +} > > We clearly need runtime PM get/put() calls around this code. Otherwise, > we're dependant on U-Boot leaving the clocks enabled... Even that would be futile, as the common clock framework disables all unused clocks at late boot time. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds