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From:   Vishal Sagar <vsagar@xilinx.com>
To:     Vishal Sagar <vishal.sagar@xilinx.com>,
        Hyun Kwon <hyunk@xilinx.com>,
        "laurent.pinchart@ideasonboard.com" 
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        Michal Simek <michals@xilinx.com>,
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        Dinesh Kumar <dineshk@xilinx.com>,
        Sandip Kothari <sandipk@xilinx.com>
Subject: RE: [PATCH v4 0/2] Add support for Xilinx CSI2 Receiver Subsystem
Thread-Topic: [PATCH v4 0/2] Add support for Xilinx CSI2 Receiver Subsystem
Thread-Index: AQHU1dWTlxX3cEKB1kuu0S98N+Oij6YCCCNA
Date:   Fri, 8 Mar 2019 18:13:22 +0000
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Hi all,

Please ignore this patch series as I missed addressing some comments in thi=
s patch.
I will address them in the next series.=20

Regards
Vishal Sagar

> -----Original Message-----
> From: Vishal Sagar [mailto:vishal.sagar@xilinx.com]
> Sent: Friday, March 08, 2019 11:01 PM
> To: Hyun Kwon <hyunk@xilinx.com>; laurent.pinchart@ideasonboard.com;
> mchehab@kernel.org; robh+dt@kernel.org; mark.rutland@arm.com; Michal
> Simek <michals@xilinx.com>; linux-media@vger.kernel.org;
> devicetree@vger.kernel.org; sakari.ailus@linux.intel.com;
> hans.verkuil@cisco.com; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; Dinesh Kumar <dineshk@xilinx.com>; Sandip Kothari
> <sandipk@xilinx.com>
> Cc: Vishal Sagar <vishal.sagar@xilinx.com>
> Subject: [PATCH v4 0/2] Add support for Xilinx CSI2 Receiver Subsystem
>=20
> Xilinx MIPI CSI-2 Receiver Subsystem
> ------------------------------------
>=20
> The Xilinx MIPI CSI-2 Receiver Subsystem Soft IP consists of a DPHY which
> gets the data, an optional I2C, a CSI-2 Receiver which parses the data an=
d
> converts it into AXIS data.
> This stream output maybe connected to a Xilinx Video Format Bridge.
> The maximum number of lanes supported is fixed in the design.
> The number of active lanes can be programmed.
> For e.g. the design may set maximum lanes as 4 but if the camera sensor h=
as
> only 1 lane then the active lanes shall be set as 1.
>=20
> The pixel format set in design acts as a filter allowing only the selecte=
d
> data type or RAW8 data packets. The D-PHY register access can be gated in
> the design. The base address of the DPHY depends on whether the internal
> Xilinx I2C controller is enabled or not in design.
>=20
> The device driver registers the MIPI CSI2 Rx Subsystem as a V4L2 sub devi=
ce
> having 2 pads. The sink pad is connected to the MIPI camera sensor and
> output pad is connected to the video node.
> Refer to xlnx,csi2rxss.txt for device tree node details.
>=20
> This driver helps configure the number of active lanes to be set, setting
> and handling interrupts and IP core enable. It logs the number of events
> occurring according to their type between streaming ON and OFF.
> It generates a v4l2 event for each short packet data received.
> The application can then dequeue this event and get the requisite data
> from the event structure.
>=20
> It adds new V4L2 controls which are used to get the event counter values
> and reset the subsystem.
>=20
> The Xilinx CSI-2 Rx Subsystem outputs an AXI4 Stream data which can be
> used for image processing. This data follows the video formats mentioned
> in Xilinx UG934 when the Video Format Bridge.
>=20
> v4
> - 1/2
>   - Added reviewed by Hyun Kwon
> - 2/2
>   - Removed irq member from core structure
>   - Consolidated IP config prints in xcsi2rxss_log_ipconfig()
>   - Return -EINVAL in case of invalid ioctl
>   - Code formatting
>   - Added reviewed by Hyun Kwon
>=20
> v3
> - 1/2
>   - removed interrupt parent as suggested by Rob
>   - removed dphy clock
>   - moved vfb to optional properties
>   - Added required and optional port properties section
>   - Added endpoint property section
> - 2/2
>  - Fixed comments given by Hyun.
>  - Removed DPHY 200 MHz clock. This will be controlled by DPHY driver
>  - Minor code formatting
>  - en_csi_v20 and vfb members removed from struct and made local to dt
> parsing
>  - lock description updated
>  - changed to ratelimited type for all dev prints in irq handler
>  - Removed YUV 422 10bpc media format
>=20
> v2
> - 1/2
>   - updated the compatible string to latest version supported
>   - removed DPHY related parameters
>   - added CSI v2.0 related property (including VCX for supporting upto 16
>     virtual channels).
>   - modified csi-pxl-format from string to unsigned int type where the va=
lue
>     is as per the CSI specification
>   - Defined port 0 and port 1 as sink and source ports.
>   - Removed max-lanes property as suggested by Rob and Sakari
>=20
> - 2/2
>   - Fixed comments given by Hyun and Sakari.
>   - Made all bitmask using BIT() and GENMASK()
>   - Removed unused definitions
>   - Removed DPHY access. This will be done by separate DPHY PHY driver.
>   - Added support for CSI v2.0 for YUV 422 10bpc, RAW16, RAW20 and extra
>     virtual channels
>   - Fixed the ports as sink and source
>   - Now use the v4l2fwnode API to get number of data-lanes
>   - Added clock framework support
>   - Removed the close() function
>   - updated the set format function
>   - Support only VFB enabled config
>=20
> Vishal Sagar (2):
>   media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem
>   media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver
>=20
>  .../bindings/media/xilinx/xlnx,csi2rxss.txt        |  123 ++
>  drivers/media/platform/xilinx/Kconfig              |   10 +
>  drivers/media/platform/xilinx/Makefile             |    1 +
>  drivers/media/platform/xilinx/xilinx-csi2rxss.c    | 1557
> ++++++++++++++++++++
>  include/uapi/linux/xilinx-v4l2-controls.h          |   14 +
>  include/uapi/linux/xilinx-v4l2-events.h            |   25 +
>  6 files changed, 1730 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
>  create mode 100644 drivers/media/platform/xilinx/xilinx-csi2rxss.c
>  create mode 100644 include/uapi/linux/xilinx-v4l2-events.h
>=20
> --
> 2.7.4