Received: by 2002:ac0:950c:0:0:0:0:0 with SMTP id f12csp930457imc; Mon, 11 Mar 2019 02:41:26 -0700 (PDT) X-Google-Smtp-Source: APXvYqzOLG9atybm7tWyZwCXQMUxmtTHnx/DO2IEjQ3T4RexIHI+wXDK4hwXobdbcfzabSA37epi X-Received: by 2002:a62:13da:: with SMTP id 87mr31914757pft.173.1552297286441; Mon, 11 Mar 2019 02:41:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1552297286; cv=none; d=google.com; s=arc-20160816; b=LJ9UyeUTHb7KnX6ug+6yi+BwVRVAcJUMYwGl5XEFTIFI76nQaiV8aaDvUv4qIrKayr S5FI0DSGQ4MiebP92UF5Cdebf7oeskLBVl394c3sGHIByN9l/kqFwsfqQ/tOz/TnJf2P jiptEuT2O3eoAovhT8W++RxKptH1OAthxk5hZY/rTB87vK2q1YKzUWKpm/gQStXr7R2Q nQCc5DN6YAsJoXzSUh7xKFBeZ6bOohMmifQ/MxezeeakAi7EEHKU4DTWMkXXvu1d+Shn Hesvv/Z5UyXIWqnoCZyrED3H/O8hAMKxs94AB6/GGDoh9f5XbWx+ISGwjwdOSAM+xkbl OEBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:cc:to:subject :message-id:date:from:in-reply-to:references:mime-version :dkim-signature; bh=m10vH7VhrLXBtuRmbQQzufuUhuoAzkMO8SrlxsRrKXo=; b=XfsnC5aJTV0dNGkgxbCJOzH0x0oyGTbVfju92la1az2QjvlUVoXHkAZcUsyVxDZqgI Fy5tU/w6XzA0hm2vZA+cQEHXCjymh5VrXfcx+FxzTUQ/4o3r6Cs9ViRjDNCix6+JksvV ziqCTiZgse7eUU0UU5uPN2CpnndfTGJsl7ACUGRX+JIX9d2PbxUVbKCENj9zv8EZEjY5 GtkhNbnWQghCLERTWZ9ffHqjx+vrE+8nY/Vbyl6OWAEtzX9gVZwNPQGSjSAcra1A+1hV +F6qL5+kuOUICV0aKAYxHasX1Jn36PnEXGYVfXvWkAK3Xv5n25uCukEjM7wQItzEciY/ zw+A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=aQyyrIFh; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y10si4482809pgh.577.2019.03.11.02.41.10; Mon, 11 Mar 2019 02:41:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=aQyyrIFh; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727418AbfCKJkE (ORCPT + 99 others); Mon, 11 Mar 2019 05:40:04 -0400 Received: from mail-ot1-f68.google.com ([209.85.210.68]:35532 "EHLO mail-ot1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727386AbfCKJkB (ORCPT ); Mon, 11 Mar 2019 05:40:01 -0400 Received: by mail-ot1-f68.google.com with SMTP id z19so3342444otm.2 for ; Mon, 11 Mar 2019 02:39:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=m10vH7VhrLXBtuRmbQQzufuUhuoAzkMO8SrlxsRrKXo=; b=aQyyrIFhTttAT8JZQorU4f0/QVQOJ3rQJAc8+E4snl64tzIwba9RVgkL0kGcN5FUyp SX+M+PwdgcoPNrQrYzbn27PhhPzS4AuRvEI/W7953uGsaxumiRu0kFhIImCpfAYTJr/Q HV+EmvLj6/Zitz0QVlGnMH2nLA3V/lU0xpdzy13NkedRQKMcj1SEOHsDnM2IRUu3xRid V7KAswGvtnDaqUd4TRANoKyfEIExypC0pLbx7FKIm9duxJ1cipVzfv/IDue66CBog6r0 ZfFL4MzyPubv8At8JYJyJXs0OIg694Z0pDOC2HkebRqdogINHqIL+YYM17Q6MM6Vj4Bq /5iQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=m10vH7VhrLXBtuRmbQQzufuUhuoAzkMO8SrlxsRrKXo=; b=k9yq8O3jd/wVy6xsJdzCYsFQqxZcD8rDIQUdA4np/NqNBAy5M841BqU+C6M/Gy3ejc aUEM9ApGjQZYUfMV3FoTU07/mSbdoovfleps4ydWJeU6yShxvUFBsPmZhjuUTlJAHORk vt78PLr7bq6QEyRF/Ojuo6oo1R1xLzbc+xxnkfyl3K+EGkc/6nvrB0Ka30wy5kpAC0Qs /8Yy1/YPRuz406WUgBHOawN5mvviGx5MQBAIoGZVyP1+JpRsPKomxq3FzQUD+tDFlqTz D3jIyeVsFFjV7zO8XVzmmY26MLr1i8AvbYjt0dd49S7bqzRLnbepmTmyBPoX5ZDwmbQ6 JlyA== X-Gm-Message-State: APjAAAXJcbYdQh62ftLOccI9OItd9qYopCGvXnAn1gOxyIvBqhweYlQo vsyEXlPwFx86Cjt7TjPeQsF+Yg8NVPGSltYHyqPGzQ== X-Received: by 2002:a9d:6c8c:: with SMTP id c12mr19374297otr.27.1552297199062; Mon, 11 Mar 2019 02:39:59 -0700 (PDT) MIME-Version: 1.0 References: <20190307103348.1591457-1-arnd@arndb.de> In-Reply-To: <20190307103348.1591457-1-arnd@arndb.de> From: Bartosz Golaszewski Date: Mon, 11 Mar 2019 10:39:48 +0100 Message-ID: Subject: Re: [PATCH] gpio: omap: avoid clang warning To: Arnd Bergmann Cc: Grygorii Strashko , Santosh Shilimkar , Kevin Hilman , Linus Walleij , Nick Desaulniers , Tony Lindgren , Janusz Krzysztofik , Wolfram Sang , Linux-OMAP , linux-gpio , LKML Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org czw., 7 mar 2019 o 11:39 Arnd Bergmann napisa=C5=82(a): > > clang warns about a tentative array definition in the gpio-omap driver: > > drivers/gpio/gpio-omap.c:1282:34: error: tentative array definition assum= ed to have one element [-Werror] > static const struct of_device_id omap_gpio_match[]; > > It's best to just reorder the entire file to avoid forward declarations, > which lets us use the regular declaration. To do this, the unnecessary > CONFIG_OF check must also be removed. > > Signed-off-by: Arnd Bergmann > --- > drivers/gpio/gpio-omap.c | 549 +++++++++++++++++++-------------------- > 1 file changed, 267 insertions(+), 282 deletions(-) > > diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c > index f4e9921fa966..9d743563f4c1 100644 > --- a/drivers/gpio/gpio-omap.c > +++ b/drivers/gpio/gpio-omap.c > @@ -1249,196 +1249,63 @@ static int omap_gpio_chip_init(struct gpio_bank = *bank, struct irq_chip *irqc) > return ret; > } > > -static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context= ); > -static void omap_gpio_unidle(struct gpio_bank *bank); > - > -static int gpio_omap_cpu_notifier(struct notifier_block *nb, > - unsigned long cmd, void *v) > +static void omap_gpio_init_context(struct gpio_bank *p) > { > - struct gpio_bank *bank; > - unsigned long flags; > + struct omap_gpio_reg_offs *regs =3D p->regs; > + void __iomem *base =3D p->base; > > - bank =3D container_of(nb, struct gpio_bank, nb); > + p->context.ctrl =3D readl_relaxed(base + regs->ctrl); > + p->context.oe =3D readl_relaxed(base + regs->direction)= ; > + p->context.wake_en =3D readl_relaxed(base + regs->wkup_en); > + p->context.leveldetect0 =3D readl_relaxed(base + regs->leveldetec= t0); > + p->context.leveldetect1 =3D readl_relaxed(base + regs->leveldetec= t1); > + p->context.risingdetect =3D readl_relaxed(base + regs->risingdete= ct); > + p->context.fallingdetect =3D readl_relaxed(base + regs->fallingde= tect); > + p->context.irqenable1 =3D readl_relaxed(base + regs->irqenable)= ; > + p->context.irqenable2 =3D readl_relaxed(base + regs->irqenable2= ); > > - raw_spin_lock_irqsave(&bank->lock, flags); > - switch (cmd) { > - case CPU_CLUSTER_PM_ENTER: > - if (bank->is_suspended) > - break; > - omap_gpio_idle(bank, true); > - break; > - case CPU_CLUSTER_PM_ENTER_FAILED: > - case CPU_CLUSTER_PM_EXIT: > - if (bank->is_suspended) > - break; > - omap_gpio_unidle(bank); > - break; > - } > - raw_spin_unlock_irqrestore(&bank->lock, flags); > + if (regs->set_dataout && p->regs->clr_dataout) > + p->context.dataout =3D readl_relaxed(base + regs->set_dat= aout); > + else > + p->context.dataout =3D readl_relaxed(base + regs->dataout= ); > > - return NOTIFY_OK; > + p->context_valid =3D true; > } > > -static const struct of_device_id omap_gpio_match[]; > - > -static int omap_gpio_probe(struct platform_device *pdev) > +static void omap_gpio_restore_context(struct gpio_bank *bank) > { > - struct device *dev =3D &pdev->dev; > - struct device_node *node =3D dev->of_node; > - const struct of_device_id *match; > - const struct omap_gpio_platform_data *pdata; > - struct resource *res; > - struct gpio_bank *bank; > - struct irq_chip *irqc; > - int ret; > - > - match =3D of_match_device(of_match_ptr(omap_gpio_match), dev); > - > - pdata =3D match ? match->data : dev_get_platdata(dev); > - if (!pdata) > - return -EINVAL; > - > - bank =3D devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL); > - if (!bank) > - return -ENOMEM; > - > - irqc =3D devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL); > - if (!irqc) > - return -ENOMEM; > - > - irqc->irq_startup =3D omap_gpio_irq_startup, > - irqc->irq_shutdown =3D omap_gpio_irq_shutdown, > - irqc->irq_ack =3D omap_gpio_ack_irq, > - irqc->irq_mask =3D omap_gpio_mask_irq, > - irqc->irq_unmask =3D omap_gpio_unmask_irq, > - irqc->irq_set_type =3D omap_gpio_irq_type, > - irqc->irq_set_wake =3D omap_gpio_wake_enable, > - irqc->irq_bus_lock =3D omap_gpio_irq_bus_lock, > - irqc->irq_bus_sync_unlock =3D gpio_irq_bus_sync_unlock, > - irqc->name =3D dev_name(&pdev->dev); > - irqc->flags =3D IRQCHIP_MASK_ON_SUSPEND; > - irqc->parent_device =3D dev; > - > - bank->irq =3D platform_get_irq(pdev, 0); > - if (bank->irq <=3D 0) { > - if (!bank->irq) > - bank->irq =3D -ENXIO; > - if (bank->irq !=3D -EPROBE_DEFER) > - dev_err(dev, > - "can't get irq resource ret=3D%d\n", bank= ->irq); > - return bank->irq; > - } > - > - bank->chip.parent =3D dev; > - bank->chip.owner =3D THIS_MODULE; > - bank->dbck_flag =3D pdata->dbck_flag; > - bank->quirks =3D pdata->quirks; > - bank->stride =3D pdata->bank_stride; > - bank->width =3D pdata->bank_width; > - bank->is_mpuio =3D pdata->is_mpuio; > - bank->non_wakeup_gpios =3D pdata->non_wakeup_gpios; > - bank->regs =3D pdata->regs; > -#ifdef CONFIG_OF_GPIO > - bank->chip.of_node =3D of_node_get(node); > -#endif > - > - if (node) { > - if (!of_property_read_bool(node, "ti,gpio-always-on")) > - bank->loses_context =3D true; > - } else { > - bank->loses_context =3D pdata->loses_context; > - > - if (bank->loses_context) > - bank->get_context_loss_count =3D > - pdata->get_context_loss_count; > - } > - > - if (bank->regs->set_dataout && bank->regs->clr_dataout) { > - bank->set_dataout =3D omap_set_gpio_dataout_reg; > - bank->set_dataout_multiple =3D omap_set_gpio_dataout_reg_= multiple; > - } else { > - bank->set_dataout =3D omap_set_gpio_dataout_mask; > - bank->set_dataout_multiple =3D > - omap_set_gpio_dataout_mask_multiple; > - } > - > - if (bank->quirks & OMAP_GPIO_QUIRK_IDLE_REMOVE_TRIGGER) { > - bank->funcs.idle_enable_level_quirk =3D > - omap2_gpio_enable_level_quirk; > - bank->funcs.idle_disable_level_quirk =3D > - omap2_gpio_disable_level_quirk; > - } > - > - raw_spin_lock_init(&bank->lock); > - raw_spin_lock_init(&bank->wa_lock); > - > - /* Static mapping, never released */ > - res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); > - bank->base =3D devm_ioremap_resource(dev, res); > - if (IS_ERR(bank->base)) { > - return PTR_ERR(bank->base); > - } > - > - if (bank->dbck_flag) { > - bank->dbck =3D devm_clk_get(dev, "dbclk"); > - if (IS_ERR(bank->dbck)) { > - dev_err(dev, > - "Could not get gpio dbck. Disable debounc= e\n"); > - bank->dbck_flag =3D false; > - } else { > - clk_prepare(bank->dbck); > - } > - } > - > - platform_set_drvdata(pdev, bank); > - > - pm_runtime_enable(dev); > - pm_runtime_get_sync(dev); > - > - if (bank->is_mpuio) > - omap_mpuio_init(bank); > - > - omap_gpio_mod_init(bank); > - > - ret =3D omap_gpio_chip_init(bank, irqc); > - if (ret) { > - pm_runtime_put_sync(dev); > - pm_runtime_disable(dev); > - if (bank->dbck_flag) > - clk_unprepare(bank->dbck); > - return ret; > - } > - > - omap_gpio_show_rev(bank); > + writel_relaxed(bank->context.wake_en, > + bank->base + bank->regs->wkup_en); > + writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl)= ; > + writel_relaxed(bank->context.leveldetect0, > + bank->base + bank->regs->leveldetect0); > + writel_relaxed(bank->context.leveldetect1, > + bank->base + bank->regs->leveldetect1); > + writel_relaxed(bank->context.risingdetect, > + bank->base + bank->regs->risingdetect); > + writel_relaxed(bank->context.fallingdetect, > + bank->base + bank->regs->fallingdetect); > + if (bank->regs->set_dataout && bank->regs->clr_dataout) > + writel_relaxed(bank->context.dataout, > + bank->base + bank->regs->set_dataout); > + else > + writel_relaxed(bank->context.dataout, > + bank->base + bank->regs->dataout); > + writel_relaxed(bank->context.oe, bank->base + bank->regs->directi= on); > > - if (bank->funcs.idle_enable_level_quirk && > - bank->funcs.idle_disable_level_quirk) { > - bank->nb.notifier_call =3D gpio_omap_cpu_notifier; > - cpu_pm_register_notifier(&bank->nb); > + if (bank->dbck_enable_mask) { > + writel_relaxed(bank->context.debounce, bank->base + > + bank->regs->debounce); > + writel_relaxed(bank->context.debounce_en, > + bank->base + bank->regs->debounce= _en); > } > > - pm_runtime_put(dev); > - > - return 0; > -} > - > -static int omap_gpio_remove(struct platform_device *pdev) > -{ > - struct gpio_bank *bank =3D platform_get_drvdata(pdev); > - > - if (bank->nb.notifier_call) > - cpu_pm_unregister_notifier(&bank->nb); > - list_del(&bank->node); > - gpiochip_remove(&bank->chip); > - pm_runtime_disable(&pdev->dev); > - if (bank->dbck_flag) > - clk_unprepare(bank->dbck); > - > - return 0; > + writel_relaxed(bank->context.irqenable1, > + bank->base + bank->regs->irqenable); > + writel_relaxed(bank->context.irqenable2, > + bank->base + bank->regs->irqenable2); > } > > -static void omap_gpio_restore_context(struct gpio_bank *bank); > - > static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context= ) > { > struct device *dev =3D bank->chip.parent; > @@ -1479,8 +1346,6 @@ static void omap_gpio_idle(struct gpio_bank *bank, = bool may_lose_context) > omap_gpio_dbck_disable(bank); > } > > -static void omap_gpio_init_context(struct gpio_bank *p); > - > static void omap_gpio_unidle(struct gpio_bank *bank) > { > struct device *dev =3D bank->chip.parent; > @@ -1574,113 +1439,33 @@ static void omap_gpio_unidle(struct gpio_bank *b= ank) > bank->workaround_enabled =3D false; > } > > -static void omap_gpio_init_context(struct gpio_bank *p) > +static int gpio_omap_cpu_notifier(struct notifier_block *nb, > + unsigned long cmd, void *v) > { > - struct omap_gpio_reg_offs *regs =3D p->regs; > - void __iomem *base =3D p->base; > + struct gpio_bank *bank; > + unsigned long flags; > > - p->context.ctrl =3D readl_relaxed(base + regs->ctrl); > - p->context.oe =3D readl_relaxed(base + regs->direction)= ; > - p->context.wake_en =3D readl_relaxed(base + regs->wkup_en); > - p->context.leveldetect0 =3D readl_relaxed(base + regs->leveldetec= t0); > - p->context.leveldetect1 =3D readl_relaxed(base + regs->leveldetec= t1); > - p->context.risingdetect =3D readl_relaxed(base + regs->risingdete= ct); > - p->context.fallingdetect =3D readl_relaxed(base + regs->fallingde= tect); > - p->context.irqenable1 =3D readl_relaxed(base + regs->irqenable)= ; > - p->context.irqenable2 =3D readl_relaxed(base + regs->irqenable2= ); > + bank =3D container_of(nb, struct gpio_bank, nb); > > - if (regs->set_dataout && p->regs->clr_dataout) > - p->context.dataout =3D readl_relaxed(base + regs->set_dat= aout); > - else > - p->context.dataout =3D readl_relaxed(base + regs->dataout= ); > + raw_spin_lock_irqsave(&bank->lock, flags); > + switch (cmd) { > + case CPU_CLUSTER_PM_ENTER: > + if (bank->is_suspended) > + break; > + omap_gpio_idle(bank, true); > + break; > + case CPU_CLUSTER_PM_ENTER_FAILED: > + case CPU_CLUSTER_PM_EXIT: > + if (bank->is_suspended) > + break; > + omap_gpio_unidle(bank); > + break; > + } > + raw_spin_unlock_irqrestore(&bank->lock, flags); > > - p->context_valid =3D true; > -} > - > -static void omap_gpio_restore_context(struct gpio_bank *bank) > -{ > - writel_relaxed(bank->context.wake_en, > - bank->base + bank->regs->wkup_en); > - writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl)= ; > - writel_relaxed(bank->context.leveldetect0, > - bank->base + bank->regs->leveldetect0); > - writel_relaxed(bank->context.leveldetect1, > - bank->base + bank->regs->leveldetect1); > - writel_relaxed(bank->context.risingdetect, > - bank->base + bank->regs->risingdetect); > - writel_relaxed(bank->context.fallingdetect, > - bank->base + bank->regs->fallingdetect); > - if (bank->regs->set_dataout && bank->regs->clr_dataout) > - writel_relaxed(bank->context.dataout, > - bank->base + bank->regs->set_dataout); > - else > - writel_relaxed(bank->context.dataout, > - bank->base + bank->regs->dataout); > - writel_relaxed(bank->context.oe, bank->base + bank->regs->directi= on); > - > - if (bank->dbck_enable_mask) { > - writel_relaxed(bank->context.debounce, bank->base + > - bank->regs->debounce); > - writel_relaxed(bank->context.debounce_en, > - bank->base + bank->regs->debounce= _en); > - } > - > - writel_relaxed(bank->context.irqenable1, > - bank->base + bank->regs->irqenable); > - writel_relaxed(bank->context.irqenable2, > - bank->base + bank->regs->irqenable2); > -} > - > -static int __maybe_unused omap_gpio_runtime_suspend(struct device *dev) > -{ > - struct gpio_bank *bank =3D dev_get_drvdata(dev); > - unsigned long flags; > - int error =3D 0; > - > - raw_spin_lock_irqsave(&bank->lock, flags); > - /* Must be idled only by CPU_CLUSTER_PM_ENTER? */ > - if (bank->irq_usage) { > - error =3D -EBUSY; > - goto unlock; > - } > - omap_gpio_idle(bank, true); > - bank->is_suspended =3D true; > -unlock: > - raw_spin_unlock_irqrestore(&bank->lock, flags); > - > - return error; > -} > - > -static int __maybe_unused omap_gpio_runtime_resume(struct device *dev) > -{ > - struct gpio_bank *bank =3D dev_get_drvdata(dev); > - unsigned long flags; > - int error =3D 0; > - > - raw_spin_lock_irqsave(&bank->lock, flags); > - /* Must be unidled only by CPU_CLUSTER_PM_ENTER? */ > - if (bank->irq_usage) { > - error =3D -EBUSY; > - goto unlock; > - } > - omap_gpio_unidle(bank); > - bank->is_suspended =3D false; > -unlock: > - raw_spin_unlock_irqrestore(&bank->lock, flags); > - > - return error; > + return NOTIFY_OK; > } > > -#ifdef CONFIG_ARCH_OMAP2PLUS > -static const struct dev_pm_ops gpio_pm_ops =3D { > - SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_r= esume, > - N= ULL) > -}; > -#else > -static const struct dev_pm_ops gpio_pm_ops; > -#endif /* CONFIG_ARCH_OMAP2PLUS */ > - > -#if defined(CONFIG_OF) > static struct omap_gpio_reg_offs omap2_gpio_regs =3D { > .revision =3D OMAP24XX_GPIO_REVISION, > .direction =3D OMAP24XX_GPIO_OE, > @@ -1768,15 +1553,215 @@ static const struct of_device_id omap_gpio_match= [] =3D { > { }, > }; > MODULE_DEVICE_TABLE(of, omap_gpio_match); > + > +static int omap_gpio_probe(struct platform_device *pdev) > +{ > + struct device *dev =3D &pdev->dev; > + struct device_node *node =3D dev->of_node; > + const struct of_device_id *match; > + const struct omap_gpio_platform_data *pdata; > + struct resource *res; > + struct gpio_bank *bank; > + struct irq_chip *irqc; > + int ret; > + > + match =3D of_match_device(of_match_ptr(omap_gpio_match), dev); > + > + pdata =3D match ? match->data : dev_get_platdata(dev); > + if (!pdata) > + return -EINVAL; > + > + bank =3D devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL); > + if (!bank) > + return -ENOMEM; > + > + irqc =3D devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL); > + if (!irqc) > + return -ENOMEM; > + > + irqc->irq_startup =3D omap_gpio_irq_startup, > + irqc->irq_shutdown =3D omap_gpio_irq_shutdown, > + irqc->irq_ack =3D omap_gpio_ack_irq, > + irqc->irq_mask =3D omap_gpio_mask_irq, > + irqc->irq_unmask =3D omap_gpio_unmask_irq, > + irqc->irq_set_type =3D omap_gpio_irq_type, > + irqc->irq_set_wake =3D omap_gpio_wake_enable, > + irqc->irq_bus_lock =3D omap_gpio_irq_bus_lock, > + irqc->irq_bus_sync_unlock =3D gpio_irq_bus_sync_unlock, > + irqc->name =3D dev_name(&pdev->dev); > + irqc->flags =3D IRQCHIP_MASK_ON_SUSPEND; > + irqc->parent_device =3D dev; > + > + bank->irq =3D platform_get_irq(pdev, 0); > + if (bank->irq <=3D 0) { > + if (!bank->irq) > + bank->irq =3D -ENXIO; > + if (bank->irq !=3D -EPROBE_DEFER) > + dev_err(dev, > + "can't get irq resource ret=3D%d\n", bank= ->irq); > + return bank->irq; > + } > + > + bank->chip.parent =3D dev; > + bank->chip.owner =3D THIS_MODULE; > + bank->dbck_flag =3D pdata->dbck_flag; > + bank->quirks =3D pdata->quirks; > + bank->stride =3D pdata->bank_stride; > + bank->width =3D pdata->bank_width; > + bank->is_mpuio =3D pdata->is_mpuio; > + bank->non_wakeup_gpios =3D pdata->non_wakeup_gpios; > + bank->regs =3D pdata->regs; > +#ifdef CONFIG_OF_GPIO > + bank->chip.of_node =3D of_node_get(node); > #endif > > + if (node) { > + if (!of_property_read_bool(node, "ti,gpio-always-on")) > + bank->loses_context =3D true; > + } else { > + bank->loses_context =3D pdata->loses_context; > + > + if (bank->loses_context) > + bank->get_context_loss_count =3D > + pdata->get_context_loss_count; > + } > + > + if (bank->regs->set_dataout && bank->regs->clr_dataout) { > + bank->set_dataout =3D omap_set_gpio_dataout_reg; > + bank->set_dataout_multiple =3D omap_set_gpio_dataout_reg_= multiple; > + } else { > + bank->set_dataout =3D omap_set_gpio_dataout_mask; > + bank->set_dataout_multiple =3D > + omap_set_gpio_dataout_mask_multiple; > + } > + > + if (bank->quirks & OMAP_GPIO_QUIRK_IDLE_REMOVE_TRIGGER) { > + bank->funcs.idle_enable_level_quirk =3D > + omap2_gpio_enable_level_quirk; > + bank->funcs.idle_disable_level_quirk =3D > + omap2_gpio_disable_level_quirk; > + } > + > + raw_spin_lock_init(&bank->lock); > + raw_spin_lock_init(&bank->wa_lock); > + > + /* Static mapping, never released */ > + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); > + bank->base =3D devm_ioremap_resource(dev, res); > + if (IS_ERR(bank->base)) { > + return PTR_ERR(bank->base); > + } > + > + if (bank->dbck_flag) { > + bank->dbck =3D devm_clk_get(dev, "dbclk"); > + if (IS_ERR(bank->dbck)) { > + dev_err(dev, > + "Could not get gpio dbck. Disable debounc= e\n"); > + bank->dbck_flag =3D false; > + } else { > + clk_prepare(bank->dbck); > + } > + } > + > + platform_set_drvdata(pdev, bank); > + > + pm_runtime_enable(dev); > + pm_runtime_get_sync(dev); > + > + if (bank->is_mpuio) > + omap_mpuio_init(bank); > + > + omap_gpio_mod_init(bank); > + > + ret =3D omap_gpio_chip_init(bank, irqc); > + if (ret) { > + pm_runtime_put_sync(dev); > + pm_runtime_disable(dev); > + if (bank->dbck_flag) > + clk_unprepare(bank->dbck); > + return ret; > + } > + > + omap_gpio_show_rev(bank); > + > + if (bank->funcs.idle_enable_level_quirk && > + bank->funcs.idle_disable_level_quirk) { > + bank->nb.notifier_call =3D gpio_omap_cpu_notifier; > + cpu_pm_register_notifier(&bank->nb); > + } > + > + pm_runtime_put(dev); > + > + return 0; > +} > + > +static int omap_gpio_remove(struct platform_device *pdev) > +{ > + struct gpio_bank *bank =3D platform_get_drvdata(pdev); > + > + if (bank->nb.notifier_call) > + cpu_pm_unregister_notifier(&bank->nb); > + list_del(&bank->node); > + gpiochip_remove(&bank->chip); > + pm_runtime_disable(&pdev->dev); > + if (bank->dbck_flag) > + clk_unprepare(bank->dbck); > + > + return 0; > +} > + > +static int __maybe_unused omap_gpio_runtime_suspend(struct device *dev) > +{ > + struct gpio_bank *bank =3D dev_get_drvdata(dev); > + unsigned long flags; > + int error =3D 0; > + > + raw_spin_lock_irqsave(&bank->lock, flags); > + /* Must be idled only by CPU_CLUSTER_PM_ENTER? */ > + if (bank->irq_usage) { > + error =3D -EBUSY; > + goto unlock; > + } > + omap_gpio_idle(bank, true); > + bank->is_suspended =3D true; > +unlock: > + raw_spin_unlock_irqrestore(&bank->lock, flags); > + > + return error; > +} > + > +static int __maybe_unused omap_gpio_runtime_resume(struct device *dev) > +{ > + struct gpio_bank *bank =3D dev_get_drvdata(dev); > + unsigned long flags; > + int error =3D 0; > + > + raw_spin_lock_irqsave(&bank->lock, flags); > + /* Must be unidled only by CPU_CLUSTER_PM_ENTER? */ > + if (bank->irq_usage) { > + error =3D -EBUSY; > + goto unlock; > + } > + omap_gpio_unidle(bank); > + bank->is_suspended =3D false; > +unlock: > + raw_spin_unlock_irqrestore(&bank->lock, flags); > + > + return error; > +} > + > +static const struct dev_pm_ops gpio_pm_ops =3D { > + SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_r= esume, > + N= ULL) > +}; > + > static struct platform_driver omap_gpio_driver =3D { > .probe =3D omap_gpio_probe, > .remove =3D omap_gpio_remove, > .driver =3D { > .name =3D "omap_gpio", > .pm =3D &gpio_pm_ops, > - .of_match_table =3D of_match_ptr(omap_gpio_match), > + .of_match_table =3D omap_gpio_match, This doesn't seem like a logical part of this commit. Can you send a separate patch? Other than that, looks good to me. Bart > }, > }; > > -- > 2.20.0 >