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Mon, 11 Mar 2019 22:24:14 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=mXyH0iMdQTNu69pcdyxJt851tpAl5j0EqDhU9ffFz04=; b=PiGUTdC51Oy0ILIdXdl+irZS8rieb7lp9RItMSw/MyVHk7JwnyGVkbhWVI8VgrII/lckeagWBVWmBfahXzIfr/NJ8DpoOriTe39HE5wt68rJFgJ6VIuOeRsBG1oNDm4sSkqn8U5/Gpkjy8OKIeHsIDEbVNHZBQVMocfVnVyGNVI= Received: from DB3PR0402MB3916.eurprd04.prod.outlook.com (52.134.72.18) by DB3PR0402MB3707.eurprd04.prod.outlook.com (52.134.65.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1686.18; Tue, 12 Mar 2019 02:24:08 +0000 Received: from DB3PR0402MB3916.eurprd04.prod.outlook.com ([fe80::1cb4:3e1c:fc85:7ed7]) by DB3PR0402MB3916.eurprd04.prod.outlook.com ([fe80::1cb4:3e1c:fc85:7ed7%2]) with mapi id 15.20.1686.021; Tue, 12 Mar 2019 02:24:08 +0000 From: Anson Huang To: "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "kernel@pengutronix.de" , "festevam@gmail.com" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" CC: dl-linux-imx Subject: [PATCH V5 1/4] dt-bindings: memory-controllers: freescale: add MMDC binding doc Thread-Topic: [PATCH V5 1/4] dt-bindings: memory-controllers: freescale: add MMDC binding doc Thread-Index: AQHU2HqsZ6aEQ4hxA02MUUfLD04Ndw== Date: Tue, 12 Mar 2019 02:24:08 +0000 Message-ID: <1552357127-1283-1-git-send-email-Anson.Huang@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK2P15301CA0009.APCP153.PROD.OUTLOOK.COM (2603:1096:202:1::19) To DB3PR0402MB3916.eurprd04.prod.outlook.com (2603:10a6:8:10::18) authentication-results: spf=none (sender IP is ) smtp.mailfrom=anson.huang@nxp.com; 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received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: ng1qQkgVyA2SnAyJHPEqGNnNyDz+86Fbbjf7rV4A8qXH7WlPOAQxXBIQTScTeoHOa1nigALunrP+t9M6oCLwXnO2uqiKl6l6+/lv5yTP/Nc5pAa4NZUSV8AhpxMznZRdAatqOyRDxMXT7armTJL0QDxMMsfZKlXXSdw4HM2FqvkTRLVuCri0fBnFU3AT7sieuY6y86hARLecwTdAIBoAafVUv5goeWAhzsLavbGvJhCTtaoakMI0DrT4ctCmAn3c5uKNEz/O3pFMcgtjMOFWa4v5+mq4JhBkJxiyQ7yYETpPq+ufDV0SzJqQqfC6gC+GWxyQpxVfUnD6R9+btmpXSGg2lb9Y1CfKqAropgnc799e3N0oPrDYzWqzh0/Qa7oCqiZX/mRNiWUOeUE+8yFwFQkI0iAAGcgKkc5yIEIx3H0= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3c276ca2-2cc2-40b4-cf78-08d6a691ce60 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Mar 2019 02:24:08.5315 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0402MB3707 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Freescale MMDC (Multi Mode DDR Controller) driver is supported since i.MX6Q, but not yet documented, this patch adds binding doc for MMDC module driver. Signed-off-by: Anson Huang --- Changes since V4: - update mmdc1 example. --- .../bindings/memory-controllers/fsl/mmdc.txt | 35 ++++++++++++++++++= ++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/fs= l/mmdc.txt diff --git a/Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.= txt b/Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.txt new file mode 100644 index 0000000..bcc36c5 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.txt @@ -0,0 +1,35 @@ +Freescale Multi Mode DDR controller (MMDC) + +Required properties : +- compatible : should be one of following: + for i.MX6Q/i.MX6DL: + - "fsl,imx6q-mmdc"; + for i.MX6QP: + - "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc"; + for i.MX6SL: + - "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc"; + for i.MX6SLL: + - "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc"; + for i.MX6SX: + - "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc"; + for i.MX6UL/i.MX6ULL/i.MX6ULZ: + - "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc"; + for i.MX7ULP: + - "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc"; +- reg : address and size of MMDC DDR controller registers + +Optional properties : +- clocks : the clock provided by the SoC to access the MMDC registers + +Example : + mmdc0: memory-controller@21b0000 { /* MMDC0 */ + compatible =3D "fsl,imx6q-mmdc"; + reg =3D <0x021b0000 0x4000>; + clocks =3D <&clks IMX6QDL_CLK_MMDC_P0_IPG>; + }; + + mmdc1: memory-controller@21b4000 { /* MMDC1 */ + compatible =3D "fsl,imx6q-mmdc"; + reg =3D <0x021b4000 0x4000>; + status =3D "disabled"; + }; --=20 2.7.4