Received: by 2002:ac0:950c:0:0:0:0:0 with SMTP id f12csp1638803imc; Mon, 11 Mar 2019 19:36:20 -0700 (PDT) X-Google-Smtp-Source: APXvYqwlXFN3JD8aAKmkLvUcl5lC9P/qqMF+hjKdgzcJ4FHSqi7+69kvLbI0KMTHaM39oIlI9Ny0 X-Received: by 2002:a62:1303:: with SMTP id b3mr37468549pfj.147.1552358180082; Mon, 11 Mar 2019 19:36:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1552358180; cv=none; d=google.com; s=arc-20160816; b=vEywjlwreruKRVhxyozTl1pTAeT/SKZPfRC4aCvjTv953EsfRK7reM6OnRSLQI9N/2 gxjWiPYcr8t7APGUfKYIT7X8V+1TPLikw54K2x8unRLhx98Nle8+d75wPCTNFaqqPM4D suAVQKlC8NdibXvBVs+qEkTnGCS6vlSgm8D0CneaTlyytJPdcZMVYfLjZFBTNurBUc9E Z06XPvvjvz6cWa+/QoK94OpJFAdBuVxp7dMeNzP5ztXqCpjZfT8tAzGymBIaBQc/1B2o n3tRsB4Bpx252Z5nYvNvR3iiPC/4/K2pxLTDRYi1YbXrqkdtYcJDDwLPl4DXhy5fX/p5 +FTw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:dkim-signature; bh=r3wMeIYDHFPCDSec/vs9fah6iy98pJ3kn5/N76rO+vI=; b=gSYg6/KGj6QYl7x+sY2TXj/J7AtamaEs9sQ4fKBDz7S4KkBNpwG7plRoEgdXHzKjHw fhwXoqdfmINLJk9mdGfOkUSq9PZ6EbDfJODEqrhPA9zk0Qodh1R8v+yzS3ux1vN5+coB noMBsJn/E4YXrEdPfE04UCl9qxAtctTzo3JeTF4/3ANinXWF/asUFLCFHJWo7lQMOUYC wnpbbnN5nnd88qyyqffVhpkYkZ0MIXwA41+1nwcuZhUO41f1TjnqLNeg6lUENjdBn5fy v6gel3ryrqI0z4dxW4xXqFJUovrN8ZHASvtTp5FsAEiQff3jteO+H8SWmObDYEO/aKdw 3TFw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=qAXFgJeY; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 37si4486535ple.250.2019.03.11.19.36.00; Mon, 11 Mar 2019 19:36:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=qAXFgJeY; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726792AbfCLCfj (ORCPT + 99 others); Mon, 11 Mar 2019 22:35:39 -0400 Received: from mail-wr1-f68.google.com ([209.85.221.68]:39894 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726657AbfCLCfi (ORCPT ); Mon, 11 Mar 2019 22:35:38 -0400 Received: by mail-wr1-f68.google.com with SMTP id p8so954768wrq.6; Mon, 11 Mar 2019 19:35:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=r3wMeIYDHFPCDSec/vs9fah6iy98pJ3kn5/N76rO+vI=; b=qAXFgJeYvSLxt3UnWixuiOwE3JC47i3kaoh3YgsIvtj58uXrGCfiwF4jw9di2I5Qph ldN08FrLNRxRweCHDhGMu73v5r61NxebvwPNr3kxEqlhx2kBFv4to2lWonkXyKkb+to6 rXm7byY6aTs8xwtv+8yn2g3BoqagrsjthcPSpqUgCI0OUzA0W/wCdswhdNxBTvxJCEsW 2rSLOjsC7HDNGE7xOh1iO3T8ThQqU+KFtY21JzeNWSOozoXGLWuWalV9VtKTNDAjyktw SrcZviFHHnMdky+1HFr9X/g9zbYRsccVTMBzqAftq1gQrzNnIxXvq+zTx1MtfakysJJa b0YA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=r3wMeIYDHFPCDSec/vs9fah6iy98pJ3kn5/N76rO+vI=; b=Wt+5xvhxEaGxjVknEjAkF2Ek0RFpOh9v8KQ3vzh30Zl2H9K0yKtcPhDh1F16PEecZL hua4ZcuGIdCUgoyb1mUH3VQQWR6dB8tOdRLLDsn9GDwGgrZJLT73pA6Dox95gmDHm8Uq RrbsxiTKYrkpvOQuHlABZbqXCiwFnSSHAvMp7HhgDFkRHQMsBsiwoZad2qnF5Rqpmkei SmJFWiry33pjyCEJtOcHOLfzoOYC9WDnOebDyQgWiZKEwgWEDsGVEZ3l/HlPEqsvn1ki hsUaR0s1tv7r4eMvPbYA7vG0W6/BrydGIVh3cHAA3fsaLiwNC8DOuOgdutNPhF2CUL1N Ok/Q== X-Gm-Message-State: APjAAAVa4+PvESdYI5RydqBlgeuXJvnt08lMclJulApLQS3P33P3WWmu 3+CHz1ees8W8tK9/yBvmXOLnlCYHRdKeDFU1re8= X-Received: by 2002:adf:e548:: with SMTP id z8mr22782471wrm.52.1552358136399; Mon, 11 Mar 2019 19:35:36 -0700 (PDT) MIME-Version: 1.0 References: <20190311213124.29325-1-angus@akkea.ca> In-Reply-To: <20190311213124.29325-1-angus@akkea.ca> From: Andrey Smirnov Date: Mon, 11 Mar 2019 19:35:25 -0700 Message-ID: Subject: Re: [PATCH] arm64: dts: fsl: imx8mq: enable the thermal management unit (TMU) To: "Angus Ainslie (Purism)" Cc: Mark Rutland , Rob Herring , Shawn Guo , Fabio Estevam , Sascha Hauer , Lucas Stach , Abel Vesa , daniel.baluta@nxp.com, agx@sigxcpu.org, dl-linux-imx , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , linux-kernel Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Mar 11, 2019 at 2:35 PM Angus Ainslie (Purism) wrote: > > These are the TMU nodes from the NXP vendor kernel > Hey Angus, TMU block supports multiple thermal zones and vendor kernel doesn't really account for that (see below). Latest version of the driver in thermal tree now actually supports that feature (mulit-sensor), so I think the code in DT should reflect that as well. I recently submitted a series adding HWMON integration for TMU (https://lore.kernel.org/lkml/20190222200508.26325-1-andrew.smirnov@gmail.com/T/#u) and this is my take on this patch: https://github.com/ndreys/linux/commit/09931e3d60af0a74377307b433db97da1be31570 All of the code there is up for grabs, if you feel like using it. > Signed-off-by: Angus Ainslie (Purism) > --- > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 83 +++++++++++++++++++++++ > 1 file changed, 83 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > index 9155bd4784eb..087620c6e17f 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > @@ -8,6 +8,7 @@ > #include > #include > #include > +#include > #include "imx8mq-pinfunc.h" > > / { > @@ -89,6 +90,7 @@ > reg = <0x0>; > enable-method = "psci"; > next-level-cache = <&A53_L2>; > + #cooling-cells = <2>; > }; > > A53_1: cpu@1 { > @@ -210,6 +212,87 @@ > #interrupt-cells = <2>; > }; > > + tmu: tmu@30260000 { > + compatible = "fsl,imx8mq-tmu"; > + reg = <0x30260000 0x10000>; > + interrupt = ; > + little-endian; > + fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; > + fsl,tmu-calibration = <0x00000000 0x00000023 > + 0x00000001 0x00000029 > + 0x00000002 0x0000002f > + 0x00000003 0x00000035 > + 0x00000004 0x0000003d > + 0x00000005 0x00000043 > + 0x00000006 0x0000004b > + 0x00000007 0x00000051 > + 0x00000008 0x00000057 > + 0x00000009 0x0000005f > + 0x0000000a 0x00000067 > + 0x0000000b 0x0000006f > + > + 0x00010000 0x0000001b > + 0x00010001 0x00000023 > + 0x00010002 0x0000002b > + 0x00010003 0x00000033 > + 0x00010004 0x0000003b > + 0x00010005 0x00000043 > + 0x00010006 0x0000004b > + 0x00010007 0x00000055 > + 0x00010008 0x0000005d > + 0x00010009 0x00000067 > + 0x0001000a 0x00000070 > + > + 0x00020000 0x00000017 > + 0x00020001 0x00000023 > + 0x00020002 0x0000002d > + 0x00020003 0x00000037 > + 0x00020004 0x00000041 > + 0x00020005 0x0000004b > + 0x00020006 0x00000057 > + 0x00020007 0x00000063 > + 0x00020008 0x0000006f > + > + 0x00030000 0x00000015 > + 0x00030001 0x00000021 > + 0x00030002 0x0000002d > + 0x00030003 0x00000039 > + 0x00030004 0x00000045 > + 0x00030005 0x00000053 > + 0x00030006 0x0000005f > + 0x00030007 0x00000071>; > + #thermal-sensor-cells = <0>; As per #thermal-sensor-cells must be 1 (see Documentation/devicetree/bindings/thermal/qoriq-thermal.txt), since as I mentioned above there are multiple thermal zones (CPU, GPU, VPU). > + }; > + > + thermal-zones { > + cpu-thermal { > + polling-delay-passive = <250>; > + polling-delay = <2000>; > + thermal-sensors = <&tmu>; Ditto. Thanks, Andrey Smirnov