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[209.132.180.67]) by mx.google.com with ESMTP id k194si6847428pgc.94.2019.03.11.21.38.28; Mon, 11 Mar 2019 21:38:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=K0yoKnbk; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726766AbfCLEhv (ORCPT + 99 others); Tue, 12 Mar 2019 00:37:51 -0400 Received: from conssluserg-03.nifty.com ([210.131.2.82]:30664 "EHLO conssluserg-03.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725848AbfCLEhv (ORCPT ); Tue, 12 Mar 2019 00:37:51 -0400 X-Greylist: delayed 2657 seconds by postgrey-1.27 at vger.kernel.org; Tue, 12 Mar 2019 00:37:49 EDT Received: from mail-vk1-f176.google.com (mail-vk1-f176.google.com [209.85.221.176]) (authenticated) by conssluserg-03.nifty.com with ESMTP id x2C4bX7v022072; Tue, 12 Mar 2019 13:37:34 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conssluserg-03.nifty.com x2C4bX7v022072 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1552365454; bh=gGqYPnNxjzKwejtPG0Lu8ls9pEA8iEN51XnZ6DbVJeI=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=K0yoKnbkC3gLrvMny9LThbAUIEgLw21+p39EXD6Gd2jlDY5eVkFxbr/YEnTmqvpea HGg0H3Zch7W/naUbiTUd8gyyJfn2HgGCvmYdFQGwBcPC3xO7eUb5iYGukApwS0WYOd jsbCMEJtZfB6kMEeWO2bN5AdMOs5IH5PWKNMF7IlRZODCyhrIUlBY2VmFiH3chT5Vo Ul+i4Fv4bz3XOvYJTuRNDuCIJbjlI3Ceh2jJkVUSOotwWb3nYC5gdT75DwHieDL3IB pWEo6tM9NTDhLkOpZEXMSMjYMqdOI77CEZYhJDY5afJaXAEHM8mAEqAyKd+Me1nWWS PsyxUKrb7BMow== X-Nifty-SrcIP: [209.85.221.176] Received: by mail-vk1-f176.google.com with SMTP id p190so20373vke.4; Mon, 11 Mar 2019 21:37:34 -0700 (PDT) X-Gm-Message-State: APjAAAVKyfAfC87E+c7wt2GQ8rfk2mW5Vgp0v+OCbBjsWyZP2PmkeaYO Ydj4emSun+FvNOxQPLaThS4rjdXAMYJy6XW9x5E= X-Received: by 2002:a1f:1d01:: with SMTP id d1mr4639902vkd.0.1552365453262; Mon, 11 Mar 2019 21:37:33 -0700 (PDT) MIME-Version: 1.0 References: <0840d55707dacd1121659723246fa9f55737f426.1551598603.git.vilhelm.gray@gmail.com> In-Reply-To: <0840d55707dacd1121659723246fa9f55737f426.1551598603.git.vilhelm.gray@gmail.com> From: Masahiro Yamada Date: Tue, 12 Mar 2019 13:36:57 +0900 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v9 9/9] gpio: uniphier: Utilize for_each_set_clump8 macro To: William Breathitt Gray Cc: Linus Walleij , Andrew Morton , "open list:GPIO SUBSYSTEM" , linux-arch , Linux Kernel Mailing List , Andy Shevchenko , Rasmus Villemoes , bgolaszewski@baylibre.com, linux-arm-kernel Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, Mar 3, 2019 at 4:51 PM William Breathitt Gray wrote: > > Replace verbose implementation in set_multiple callback with > for_each_set_clump8 macro to simplify code and improve clarity. An > improvement in this case is that banks that are not masked will now be > skipped. > > Cc: Masahiro Yamada > Signed-off-by: William Breathitt Gray > --- > drivers/gpio/gpio-uniphier.c | 16 ++++++---------- > 1 file changed, 6 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpio/gpio-uniphier.c b/drivers/gpio/gpio-uniphier.c > index 0f662b297a95..df640cb29b9c 100644 > --- a/drivers/gpio/gpio-uniphier.c > +++ b/drivers/gpio/gpio-uniphier.c > @@ -15,9 +15,6 @@ > #include > #include > > -#define UNIPHIER_GPIO_BANK_MASK \ > - GENMASK((UNIPHIER_GPIO_LINES_PER_BANK) - 1, 0) > - > #define UNIPHIER_GPIO_IRQ_MAX_NUM 24 > > #define UNIPHIER_GPIO_PORT_DATA 0x0 /* data */ > @@ -147,15 +144,14 @@ static void uniphier_gpio_set(struct gpio_chip *chip, > static void uniphier_gpio_set_multiple(struct gpio_chip *chip, > unsigned long *mask, unsigned long *bits) > { > - unsigned int bank, shift, bank_mask, bank_bits; > - int i; > + unsigned int i; > + unsigned long bank_mask; > + unsigned int bank; > + unsigned int bank_bits; > > - for (i = 0; i < chip->ngpio; i += UNIPHIER_GPIO_LINES_PER_BANK) { > + for_each_set_clump8(i, bank_mask, mask, chip->ngpio) { > bank = i / UNIPHIER_GPIO_LINES_PER_BANK; > - shift = i % BITS_PER_LONG; > - bank_mask = (mask[BIT_WORD(i)] >> shift) & > - UNIPHIER_GPIO_BANK_MASK; > - bank_bits = bits[BIT_WORD(i)] >> shift; > + bank_bits = bitmap_get_value8(bits, chip->ngpio, i); > > uniphier_gpio_bank_write(chip, bank, UNIPHIER_GPIO_PORT_DATA, > bank_mask, bank_bits); Please do not do this. Nothing in this driver says the GPIO width is 8-bit. You are hard-coding '8-bit'. > -- > 2.21.0 > -- Best Regards Masahiro Yamada