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[209.132.180.67]) by mx.google.com with ESMTP id bi9si10391585plb.174.2019.03.13.05.26.29; Wed, 13 Mar 2019 05:26:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726627AbfCMMZ4 (ORCPT + 99 others); Wed, 13 Mar 2019 08:25:56 -0400 Received: from mga09.intel.com ([134.134.136.24]:62129 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725883AbfCMMZz (ORCPT ); Wed, 13 Mar 2019 08:25:55 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Mar 2019 05:25:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,474,1544515200"; d="scan'208";a="133958974" Received: from pg-eswbuild-angstrom-alpha.png.intel.com ([10.226.214.8]) by fmsmga007.fm.intel.com with ESMTP; 13 Mar 2019 05:25:52 -0700 From: "Hean-Loong, Ong" To: Rob Herring , Dinh Nguyen , Daniel Vetter Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, hean.loong.ong@intel.com, chin.liang.see@intel.com, Ong@vger.kernel.org Subject: [PATCHv14 0/3] Intel FPGA Video and Image Processing Suite Date: Thu, 14 Mar 2019 04:22:03 +0800 Message-Id: <20190313202206.921-1-hean.loong.ong@intel.com> X-Mailer: git-send-email 2.17.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ong, Hean Loong The FPGA FrameBuffer Soft IP could be seen as the GPU and the DRM driver patch here is allocating memory for information to be streamed from the ARM/Linux to the display port. Basically the driver just wraps the information such as the pixels to be drawn by the Sodt IP FrameBuffer 2. The piece of hardware in discussion is the SoC FPGA where Linux runs on the ARM chip and the FGPA is driven by its NIOS soft core with its own proprietary firmware. For example the application from the ARM Linux would have to write information on the /dev/fb0 with the information stored in the SDRAM to be fetched by the Framebuffer 2 Soft IP and displayed on the Display Port Monitor. Ong Hean Loong (1): ARM:socfpga-defconfig Intel FPGA Video and Image Processing Suite Ong, Hean Loong (2): ARM:dt-bindings:display Intel FPGA Video and Image Processing Suite ARM:drm ivip Intel FPGA Video and Image Processing Suite .../devicetree/bindings/display/altr,vip-fb2.txt | 63 ++++ MAINTAINERS | 9 + arch/arm/configs/socfpga_defconfig | 8 + drivers/gpu/drm/Kconfig | 2 + drivers/gpu/drm/Makefile | 1 + drivers/gpu/drm/ivip/Kconfig | 14 + drivers/gpu/drm/ivip/Makefile | 6 + drivers/gpu/drm/ivip/intel_vip_conn.c | 93 ++++++ drivers/gpu/drm/ivip/intel_vip_drv.c | 335 ++++++++++++++++++++ drivers/gpu/drm/ivip/intel_vip_drv.h | 73 +++++ 10 files changed, 604 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/altr,vip-fb2.txt create mode 100644 drivers/gpu/drm/ivip/Kconfig create mode 100644 drivers/gpu/drm/ivip/Makefile create mode 100644 drivers/gpu/drm/ivip/intel_vip_conn.c create mode 100644 drivers/gpu/drm/ivip/intel_vip_drv.c create mode 100644 drivers/gpu/drm/ivip/intel_vip_drv.h