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From:   Christina Quast <cquast@hanoverdisplays.com>
Cc:     bcousson@baylibre.com, tony@atomide.com, robh+dt@kernel.org,
        mark.rutland@arm.com, mpfj@newflow.co.uk,
        cquast@hanoverdisplays.com, linux-omap@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH 1/2] ARM: dts: am335x: Replace numeric pinmux address with macro defines
Date:   Wed, 13 Mar 2019 15:27:23 +0100
Message-Id: <20190313142724.27446-2-cquast@hanoverdisplays.com>
In-Reply-To: <20190313142724.27446-1-cquast@hanoverdisplays.com>
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The values are extraced from the "AM335x SitaraTM Processors Technical
Reference Manual", Section 9.3.1 CONTROL_MODULE Registers, based on the
file autogenerated by TI PinMux.

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
---
 include/dt-bindings/pinctrl/am335x.h | 236 +++++++++++++++++++++++++++
 1 file changed, 236 insertions(+)
 create mode 100644 include/dt-bindings/pinctrl/am335x.h

diff --git a/include/dt-bindings/pinctrl/am335x.h b/include/dt-bindings/pinctrl/am335x.h
new file mode 100644
index 000000000000..033a44efdc1e
--- /dev/null
+++ b/include/dt-bindings/pinctrl/am335x.h
@@ -0,0 +1,236 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * This header provides constants specific to AM335X pinctrl bindings.
+ *
+ * Copyright (C) 2018 Texas Instruments Incorporated
+ */
+
+#ifndef AM335X_PIN_MUX_H_
+#define AM335X_PIN_MUX_H_
+
+#define PIN_MODE(mode)		(mode)
+#define PIN_PULL_UD_EN		(0x1U << 3U)
+#define	PIN_PULL_TYPE_SEL	(0x1U << 4U)
+#define	PIN_RX_ACTIVE		(0x1U << 5U)
+#define PIN_SLEW_SLOW		(0x1U << 6U)
+
+#define AM335X_PIN_OFFSET_MIN			0x0800U
+
+#define AM335X_CONTROL_REVISION			0x0
+#define AM335X_CONTROL_HWINFO			0x4
+#define AM335X_CONTROL_SYSCONFIG		0x10
+#define AM335X_CONTROL_STATUS			0x40
+#define AM335X_CONTROL_EMIF_SDRAM_CONFIG	0x110
+#define AM335X_CORE_SLDO_CTRL			0x428
+#define AM335X_MPU_SLDO_CTRL			0x42c
+#define AM335X_CLK32KDIVRATIO_CTRL		0x444
+#define AM335X_BANDGAP_CTRL			0x448
+#define AM335X_BANDGAP_TRIM			0x44c
+#define AM335X_PLL_CLKINPULOW_CTRL		0x458
+#define AM335X_MOSC_CTRL			0x468
+#define AM335X_DEEPSLEEP_CTRL			0x470
+#define AM335X_DPLL_PWR_SW_STATUS		0x50c
+#define AM335X_DEVICE_ID			0x600
+#define AM335X_DEV_FEATURE			0x604
+#define AM335X_INIT_PRIORITY_0			0x608
+#define AM335X_INIT_PRIORITY_1			0x60c
+#define AM335X_TPTC_CFG				0x614
+#define AM335X_USB_CTRL0			0x620
+#define AM335X_USB_STS0				0x624
+#define AM335X_USB_CTRL1			0x628
+#define AM335X_USB_STS1				0x62c
+#define AM335X_MAC_ID0_LO			0x630
+#define AM335X_MAC_ID0_HI			0x634
+#define AM335X_MAC_ID1_LO			0x638
+#define AM335X_MAC_ID1_HI			0x63c
+#define AM335X_DCAN_RAMINIT			0x644
+#define AM335X_USB_WKUP_CTRL			0x648
+#define AM335X_GMII_SEL				0x650
+#define AM335X_PWMSS_CTRL			0x664
+#define AM335X_MREQPRIO_0			0x670
+#define AM335X_MREQPRIO_1			0x674
+#define AM335X_HW_EVENT_SEL_GRP1		0x690
+#define AM335X_HW_EVENT_SEL_GRP2		0x694
+#define AM335X_HW_EVENT_SEL_GRP3		0x698
+#define AM335X_HW_EVENT_SEL_GRP4		0x69c
+#define AM335X_SMRT_CTRL			0x6a0
+#define AM335X_MPUSS_HW_DEBUG_SEL		0x6a4
+#define AM335X_MPUSS_HW_DBG_INFO		0x6a8
+#define AM335X_VDD_MPU_OPP_050			0x770
+#define AM335X_VDD_MPU_OPP_100			0x774
+#define AM335X_VDD_MPU_OPP_120			0x778
+#define AM335X_VDD_MPU_OPP_TURBO		0x77c
+#define AM335X_VDD_CORE_OPP_050			0x7b8
+#define AM335X_VDD_CORE_OPP_100			0x7bc
+#define AM335X_BB_SCALE				0x7d0
+#define AM335X_USB_VID_PID			0x7f4
+#define AM335X_EFUSE_SMA			0x7fc
+#define AM335X_PIN_GPMC_AD0			0x800
+#define AM335X_PIN_GPMC_AD1			0x804
+#define AM335X_PIN_GPMC_AD2			0x808
+#define AM335X_PIN_GPMC_AD3			0x80c
+#define AM335X_PIN_GPMC_AD4			0x810
+#define AM335X_PIN_GPMC_AD5			0x814
+#define AM335X_PIN_GPMC_AD6			0x818
+#define AM335X_PIN_GPMC_AD7			0x81c
+#define AM335X_PIN_GPMC_AD8			0x820
+#define AM335X_PIN_GPMC_AD9			0x824
+#define AM335X_PIN_GPMC_AD10			0x828
+#define AM335X_PIN_GPMC_AD11			0x82c
+#define AM335X_PIN_GPMC_AD12			0x830
+#define AM335X_PIN_GPMC_AD13			0x834
+#define AM335X_PIN_GPMC_AD14			0x838
+#define AM335X_PIN_GPMC_AD15			0x83c
+#define AM335X_PIN_GPMC_A0			0x840
+#define AM335X_PIN_GPMC_A1			0x844
+#define AM335X_PIN_GPMC_A2			0x848
+#define AM335X_PIN_GPMC_A3			0x84c
+#define AM335X_PIN_GPMC_A4			0x850
+#define AM335X_PIN_GPMC_A5			0x854
+#define AM335X_PIN_GPMC_A6			0x858
+#define AM335X_PIN_GPMC_A7			0x85c
+#define AM335X_PIN_GPMC_A8			0x860
+#define AM335X_PIN_GPMC_A9			0x864
+#define AM335X_PIN_GPMC_A10			0x868
+#define AM335X_PIN_GPMC_A11			0x86c
+#define AM335X_PIN_GPMC_WAIT0			0x870
+#define AM335X_PIN_GPMC_WPN			0x874
+#define AM335X_PIN_GPMC_BEN1			0x878
+#define AM335X_PIN_GPMC_CSN0			0x87c
+#define AM335X_PIN_GPMC_CSN1			0x880
+#define AM335X_PIN_GPMC_CSN2			0x884
+#define AM335X_PIN_GPMC_CSN3			0x888
+#define AM335X_PIN_GPMC_CLK			0x88c
+#define AM335X_PIN_GPMC_ADVN_ALE		0x890
+#define AM335X_PIN_GPMC_OEN_REN			0x894
+#define AM335X_PIN_GPMC_WEN			0x898
+#define AM335X_PIN_GPMC_BEN0_CLE		0x89c
+#define AM335X_PIN_LCD_DATA0			0x8a0
+#define AM335X_PIN_LCD_DATA1			0x8a4
+#define AM335X_PIN_LCD_DATA2			0x8a8
+#define AM335X_PIN_LCD_DATA3			0x8ac
+#define AM335X_PIN_LCD_DATA4			0x8b0
+#define AM335X_PIN_LCD_DATA5			0x8b4
+#define AM335X_PIN_LCD_DATA6			0x8b8
+#define AM335X_PIN_LCD_DATA7			0x8bc
+#define AM335X_PIN_LCD_DATA8			0x8c0
+#define AM335X_PIN_LCD_DATA9			0x8c4
+#define AM335X_PIN_LCD_DATA10			0x8c8
+#define AM335X_PIN_LCD_DATA11			0x8cc
+#define AM335X_PIN_LCD_DATA12			0x8d0
+#define AM335X_PIN_LCD_DATA13			0x8d4
+#define AM335X_PIN_LCD_DATA14			0x8d8
+#define AM335X_PIN_LCD_DATA15			0x8dc
+#define AM335X_PIN_LCD_VSYNC			0x8e0
+#define AM335X_PIN_LCD_HSYNC			0x8e4
+#define AM335X_PIN_LCD_PCLK			0x8e8
+#define AM335X_PIN_LCD_AC_BIAS_EN		0x8ec
+#define AM335X_PIN_MMC0_DAT3			0x8f0
+#define AM335X_PIN_MMC0_DAT2			0x8f4
+#define AM335X_PIN_MMC0_DAT1			0x8f8
+#define AM335X_PIN_MMC0_DAT0			0x8fc
+#define AM335X_PIN_MMC0_CLK			0x900
+#define AM335X_PIN_MMC0_CMD			0x904
+#define AM335X_PIN_MII1_COL			0x908
+#define AM335X_PIN_MII1_CRS			0x90c
+#define AM335X_PIN_MII1_RX_ER			0x910
+#define AM335X_PIN_MII1_TX_EN			0x914
+#define AM335X_PIN_MII1_RX_DV			0x918
+#define AM335X_PIN_MII1_TXD3			0x91c
+#define AM335X_PIN_MII1_TXD2			0x920
+#define AM335X_PIN_MII1_TXD1			0x924
+#define AM335X_PIN_MII1_TXD0			0x928
+#define AM335X_PIN_MII1_TX_CLK			0x92c
+#define AM335X_PIN_MII1_RX_CLK			0x930
+#define AM335X_PIN_MII1_RXD3			0x934
+#define AM335X_PIN_MII1_RXD2			0x938
+#define AM335X_PIN_MII1_RXD1			0x93c
+#define AM335X_PIN_MII1_RXD0			0x940
+#define AM335X_PIN_RMII1_REF_CLK		0x944
+#define AM335X_PIN_MDIO				0x948
+#define AM335X_PIN_MDC				0x94c
+#define AM335X_PIN_SPI0_SCLK			0x950
+#define AM335X_PIN_SPI0_D0			0x954
+#define AM335X_PIN_SPI0_D1			0x958
+#define AM335X_PIN_SPI0_CS0			0x95c
+#define AM335X_PIN_SPI0_CS1			0x960
+#define AM335X_PIN_ECAP0_IN_PWM0_OUT		0x964
+#define AM335X_PIN_UART0_CTSN			0x968
+#define AM335X_PIN_UART0_RTSN			0x96c
+#define AM335X_PIN_UART0_RXD			0x970
+#define AM335X_PIN_UART0_TXD			0x974
+#define AM335X_PIN_UART1_CTSN			0x978
+#define AM335X_PIN_UART1_RTSN			0x97c
+#define AM335X_PIN_UART1_RXD			0x980
+#define AM335X_PIN_UART1_TXD			0x984
+#define AM335X_PIN_I2C0_SDA			0x988
+#define AM335X_PIN_I2C0_SCL			0x98c
+#define AM335X_PIN_MCASP0_ACLKX			0x990
+#define AM335X_PIN_MCASP0_FSX			0x994
+#define AM335X_PIN_MCASP0_AXR0			0x998
+#define AM335X_PIN_MCASP0_AHCLKR		0x99c
+#define AM335X_PIN_MCASP0_ACLKR			0x9a0
+#define AM335X_PIN_MCASP0_FSR			0x9a4
+#define AM335X_PIN_MCASP0_AXR1			0x9a8
+#define AM335X_PIN_MCASP0_AHCLKX		0x9ac
+#define AM335X_PIN_XDMA_EVENT_INTR0		0x9b0
+#define AM335X_PIN_XDMA_EVENT_INTR1		0x9b4
+#define AM335X_PIN_WARMRSTN			0x9b8
+#define AM335X_PIN_NNMI				0x9c0
+#define AM335X_PIN_TMS				0x9d0
+#define AM335X_PIN_TDI				0x9d4
+#define AM335X_PIN_TDO				0x9d8
+#define AM335X_PIN_TCK				0x9dc
+#define AM335X_PIN_TRSTN			0x9e0
+#define AM335X_PIN_EMU0				0x9e4
+#define AM335X_PIN_EMU1				0x9e8
+#define AM335X_PIN_RTC_PWRONRSTN		0x9f8
+#define AM335X_PIN_PMIC_POWER_EN		0x9fc
+#define AM335X_PIN_EXT_WAKEUP			0xa00
+#define AM335X_PIN_USB0_DRVVBUS			0xa1c
+#define AM335X_PIN_USB1_DRVVBUS			0xa34
+#define AM335X_CQDETECT_STATUS			0xe00
+#define AM335X_DDR_IO_CTRL			0xe04
+#define AM335X_VTP_CTRL				0xe0c
+#define AM335X_VREF_CTRL			0xe14
+#define AM335X_TPCC_EVT_MUX_0_3			0xf90
+#define AM335X_TPCC_EVT_MUX_4_7			0xf94
+#define AM335X_TPCC_EVT_MUX_8_11		0xf98
+#define AM335X_TPCC_EVT_MUX_12_15		0xf9c
+#define AM335X_TPCC_EVT_MUX_16_19		0xfa0
+#define AM335X_TPCC_EVT_MUX_20_23		0xfa4
+#define AM335X_TPCC_EVT_MUX_24_27		0xfa8
+#define AM335X_TPCC_EVT_MUX_28_31		0xfac
+#define AM335X_TPCC_EVT_MUX_32_35		0xfb0
+#define AM335X_TPCC_EVT_MUX_36_39		0xfb4
+#define AM335X_TPCC_EVT_MUX_40_43		0xfb8
+#define AM335X_TPCC_EVT_MUX_44_47		0xfbc
+#define AM335X_TPCC_EVT_MUX_48_51		0xfc0
+#define AM335X_TPCC_EVT_MUX_52_55		0xfc4
+#define AM335X_TPCC_EVT_MUX_56_59		0xfc8
+#define AM335X_TPCC_EVT_MUX_60_63		0xfcc
+#define AM335X_TIMER_EVT_CAPT			0xfd0
+#define AM335X_ECAP_EVT_CAPT			0xfd4
+#define AM335X_ADC_EVT_CAPT			0xfd8
+#define AM335X_RESET_ISO			0x1000
+#define AM335X_DPLL_PWR_SW_CTRL			0x1318
+#define AM335X_DDR_CKE_CTRL			0x131c
+#define AM335X_SMA2				0x1320
+#define AM335X_M3_TXEV_EOI			0x1324
+#define AM335X_IPC_MSG_REG0			0x1328
+#define AM335X_IPC_MSG_REG1			0x132c
+#define AM335X_IPC_MSG_REG2			0x1330
+#define AM335X_IPC_MSG_REG3			0x1334
+#define AM335X_IPC_MSG_REG4			0x1338
+#define AM335X_IPC_MSG_REG5			0x133c
+#define AM335X_IPC_MSG_REG6			0x1340
+#define AM335X_IPC_MSG_REG7			0x1344
+#define AM335X_DDR_CMD0_IOCTRL			0x1404
+#define AM335X_DDR_CMD1_IOCTRL			0x1408
+#define AM335X_DDR_CMD2_IOCTRL			0x140c
+#define AM335X_DDR_DATA0_IOCTRL			0x1440
+#define AM335X_DDR_DATA1_IOCTRL			0x1444
+
+#define AM335X_PIN_OFFSET_MAX			0x1320U
+
+#endif /* AM335X_PIN_MUX_H_ */
-- 
2.20.1