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Thu, 14 Mar 2019 07:02:10 -0700 From: Nava kishore Manne To: , , , , , , , , , , , , Subject: [PATCH v4 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver Date: Thu, 14 Mar 2019 19:31:22 +0530 Message-ID: <20190314140122.23372-7-nava.manne@xilinx.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190314140122.23372-1-nava.manne@xilinx.com> References: <20190314140122.23372-1-nava.manne@xilinx.com> X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(396003)(346002)(39860400002)(136003)(376002)(2980300002)(189003)(199004)(47776003)(478600001)(106002)(486006)(6666004)(356004)(50226002)(316002)(16586007)(2616005)(110136005)(76176011)(7696005)(186003)(50466002)(2906002)(51416003)(26005)(77096007)(81156014)(8676002)(48376002)(126002)(63266004)(106466001)(5660300002)(81166006)(305945005)(9786002)(36386004)(11346002)(8936002)(476003)(446003)(36756003)(2201001)(1076003)(426003)(336012)(921003)(1121003)(83996005)(2101003);DIR:OUT;SFP:1101;SCL:1;SRVR:CY4SPR00MB233;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;LANG:en;PTR:unknown-60-83.xilinx.com;MX:1;A:1; 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Signed-off-by: Nava kishore Manne --- Changes for v4: -Modified binding description as suggested by Moritz Fischer. Changes for v3: -Removed PCAP as a child node to the FW and Created an independent node since PCAP driver is a consumer not a provider. .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt new file mode 100644 index 000000000000..6d7f10775d9b --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt @@ -0,0 +1,11 @@ +Devicetree bindings for Zynq Ultrascale MPSoC FPGA Manager. +The ZynqMP SoC uses the PCAP (Processor configuration Port) to configure the +Programmable Logic (PL). The configuration uses the firmware interface. + +Required properties: +- compatible: should contain "xlnx,zynqmp-pcap-fpga" + +Example: + zynqmp_pcap: pcap { + compatible = "xlnx,zynqmp-pcap-fpga"; + }; -- 2.18.0