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Date:   Thu, 14 Mar 2019 16:46:28 +0100
From:   Maxime Ripard <maxime.ripard@bootlin.com>
To:     Icenowy Zheng <icenowy@aosc.io>
Cc:     Chen-Yu Tsai <wens@csie.org>, linux-arm-kernel@lists.infradead.org,
        linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-sunxi@googlegroups.com
Subject: Re: [PATCH] clk: sunxi-ng: f1c100s: fix USB PHY gate bit offset
Message-ID: <20190314154627.7f322sd2sd7asnnc@flea>
References: <20190314112108.6150-1-icenowy@aosc.io>
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On Thu, Mar 14, 2019 at 07:21:08PM +0800, Icenowy Zheng wrote:
> The bit offset of the USB PHY clock gate on F1C100s should be 1, not 8.
>=20
> Fix this problem.
>=20
> Fixes: 0380126eb9af ("clk: sunxi-ng: add support for suniv F1C100s SoC")
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

Applied, thanks!
Maxime

--=20
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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Content-Type: application/pgp-signature; name="signature.asc"

-----BEGIN PGP SIGNATURE-----

iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXIp3UwAKCRDj7w1vZxhR
xRr8AP9bvlecZCePreW1bagtRGj1Af3H1AzN+Y/tMKYY0foVVgEAq3HsIWN5LtV8
8XTCZGzDSbZOhPmHqKUJF7spt1sbEg0=
=DKGA
-----END PGP SIGNATURE-----

--gh35n5sikmol5ate--