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received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) authentication-results: spf=none (sender IP is ) smtp.mailfrom=anson.huang@nxp.com; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: 43PfuRxfZIH7MvSTL727wpDQnCn9BU3nAudKN+Y+z+yFrc74XAlDc7rUB0ipsJDUOYNQTaiJjKJE7iN2Sx/AXqihUN83OZGS0OtMu+FCRrORVnCGRaUxAugDvxXwWfOI1nLKorP1JWCBP4seXLp2Lt9SYuJMoUBoYVb52Xs2vXdTvNGTHaEgYSUS/ZNTdHXORJcqJMC4+OXz300xQrlrye9kMSowFfl3IzorKUyAftuDQK3m0fCCeLGdr0p/W3TfvAr3C3w978CK1uHjJeIob3okJSFldLJ049OiCzOkx7kwp6VAU32l8zUGqL5QokEoHflP5S5YX3AHFu305GGZr49YXWzQ0ncfFvxKEauMOAsiaLHsezdZZ7WTAjGg+Xo2Qo7LC58Dl+9knQoq2sZ2kDEtsD73Rd6T7FVqzOItI6k= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: a647e29e-a760-4287-6826-08d6a8dfbe12 X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Mar 2019 00:47:04.2166 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0402MB3772 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add i.MX7ULP EVK board PWM0 support. Signed-off-by: Anson Huang --- No changes. --- arch/arm/boot/dts/imx7ulp-evk.dts | 12 ++++++++++++ arch/arm/boot/dts/imx7ulp.dtsi | 10 ++++++++++ 2 files changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/imx7ulp-= evk.dts index a09026a..3f5ea18 100644 --- a/arch/arm/boot/dts/imx7ulp-evk.dts +++ b/arch/arm/boot/dts/imx7ulp-evk.dts @@ -40,6 +40,12 @@ status =3D "okay"; }; =20 +&pwm0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pwm0>; + status =3D "okay"; +}; + &usdhc0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_usdhc0>; @@ -57,6 +63,12 @@ bias-pull-up; }; =20 + pinctrl_pwm0: pwm0grp { + fsl,pins =3D < + IMX7ULP_PAD_PTF2__TPM4_CH1 0x2 + >; + }; + pinctrl_usdhc0: usdhc0grp { fsl,pins =3D < IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43 diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dts= i index fca6e50..6361c4e 100644 --- a/arch/arm/boot/dts/imx7ulp.dtsi +++ b/arch/arm/boot/dts/imx7ulp.dtsi @@ -124,6 +124,16 @@ status =3D "disabled"; }; =20 + pwm0: pwm@40250000 { + compatible =3D "fsl,imx-tpm-pwm"; + reg =3D <0x40250000 0x1000>; + assigned-clocks =3D <&pcc2 IMX7ULP_CLK_LPTPM4>; + assigned-clock-parents =3D <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; + clocks =3D <&pcc2 IMX7ULP_CLK_LPTPM4>; + #pwm-cells =3D <2>; + status =3D "disabled"; + }; + tpm5: tpm@40260000 { compatible =3D "fsl,imx7ulp-tpm"; reg =3D <0x40260000 0x1000>; --=20 2.7.4