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[209.132.180.67]) by mx.google.com with ESMTP id q61si1541224plb.245.2019.03.15.03.10.59; Fri, 15 Mar 2019 03:11:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728834AbfCOKJB (ORCPT + 99 others); Fri, 15 Mar 2019 06:09:01 -0400 Received: from mgwym02.jp.fujitsu.com ([211.128.242.41]:34938 "EHLO mgwym02.jp.fujitsu.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727920AbfCOKJB (ORCPT ); Fri, 15 Mar 2019 06:09:01 -0400 X-Greylist: delayed 668 seconds by postgrey-1.27 at vger.kernel.org; Fri, 15 Mar 2019 06:08:59 EDT Received: from yt-mxq.gw.nic.fujitsu.com (unknown [192.168.229.66]) by mgwym02.jp.fujitsu.com with smtp id 652b_f293_fc3661d2_054d_4f93_a705_8ea83e3bff46; Fri, 15 Mar 2019 18:57:49 +0900 Received: from g01jpfmpwkw03.exch.g01.fujitsu.local (g01jpfmpwkw03.exch.g01.fujitsu.local [10.0.193.57]) by yt-mxq.gw.nic.fujitsu.com (Postfix) with ESMTP id 7A99FAC00A4 for ; Fri, 15 Mar 2019 18:57:48 +0900 (JST) Received: from G01JPEXCHKW15.g01.fujitsu.local (G01JPEXCHKW15.g01.fujitsu.local [10.0.194.54]) by g01jpfmpwkw03.exch.g01.fujitsu.local (Postfix) with ESMTP id 7A4AFBD67FC; Fri, 15 Mar 2019 18:54:38 +0900 (JST) Received: from G01JPEXMBKW02.g01.fujitsu.local ([10.0.194.66]) by g01jpexchkw15 ([10.0.194.54]) with mapi id 14.03.0415.000; Fri, 15 Mar 2019 18:54:37 +0900 From: "Okamoto, Takayuki" To: 'Will Deacon' , 'Mark Rutland' , 'Catalin Marinas' , "'James Morse'" , "'linux-kernel@vger.kernel.org'" , "'linux-arm-kernel@lists.infradead.org'" CC: "Zhang, Lei" Subject: [PATCH] Make Fujitsu Erratum 010001 patch can be applied on A64FX v1r0 Thread-Topic: [PATCH] Make Fujitsu Erratum 010001 patch can be applied on A64FX v1r0 Thread-Index: AdTbE0WGecdQLNX9RXm/5RlJsG8uTw== Date: Fri, 15 Mar 2019 09:54:37 +0000 Message-ID: <5FA513F682BE7F4EAAB8EE035D5B08E44E936051@G01JPEXMBKW02> Accept-Language: ja-JP, en-US Content-Language: ja-JP X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.87.120.48] Content-Type: text/plain; charset="iso-2022-jp" MIME-Version: 1.0 X-SecurityPolicyCheck-GC: OK by FENCE-Mail X-TM-AS-MML: disable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi guys, > -----Original Message----- > From: James Morse > Sent: Wednesday, February 27, 2019 3:44 AM > To: james.morse@arm.com; linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org; Catalin Marinas > ; Mark Rutland ; Will > Deacon ; Zhang, Lei > Subject: [PATCH v5] arm64: Add workaround for Fujitsu A64FX erratum > 010001 > > +/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */ > +#define MIDR_FUJITSU_ERRATUM_010001 > MIDR_FUJITSU_A64FX > +#define MIDR_FUJITSU_ERRATUM_010001_MASK > (~MIDR_VARIANT(1)) This workaround for the erratum should be applied for both A64FX v1r0 and v0r0, however, the patch v5 is only enabled on A64FX v0r0(MIDR.Variant == 0 && MIDR.Revision == 0). This issue is caused by the macro MIDR_FUJITSU_ERRATUM_010001_MASK. I have tested on both A64FX v1r0 and v0r0. This new patch will effect only for A64FX. -- Changed to be applied for not only A64FX v0r0 but also v1r0. Signed-off-by: Zhang Lei --- arch/arm64/include/asm/cputype.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 2afb133..1fb47b5 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -129,7 +129,7 @@ /* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */ #define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX -#define MIDR_FUJITSU_ERRATUM_010001_MASK (~MIDR_VARIANT(1)) +#define MIDR_FUJITSU_ERRATUM_010001_MASK (~(0x1 << MIDR_VARIANT_SHIFT)) #define TCR_CLEAR_FUJITSU_ERRATUM_010001 (TCR_NFD1 | TCR_NFD0) #ifndef __ASSEMBLY__ -- 1.8.3.1 Best Regards, Takayuki Okamoto