Received: by 2002:ac0:950e:0:0:0:0:0 with SMTP id f14csp1333263imc; Sun, 17 Mar 2019 10:50:37 -0700 (PDT) X-Google-Smtp-Source: APXvYqyWuUHGalf2r+luVp46t8SY4C7bxjqzAYGP2qwsx1NXwyJWJCPQ8jhHfLzpCeHgGEQjm6BY X-Received: by 2002:a17:902:a7:: with SMTP id a36mr15762364pla.267.1552845037306; Sun, 17 Mar 2019 10:50:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1552845037; cv=none; d=google.com; s=arc-20160816; b=N67wfcIw3huUEb2JpKJ8AryrfrZnyKb+MDN4UXJCozuPfhog/bTqrjj4ywxPABIymI TPRG0gh/IgDyFE24I+5N7S5lUKZPWcufaOY2NaNuu470DnxvL3DgLVmr5FkEwuPU4BVa K2QOr2D4togKsbi/4j/n+0Mqbp4i4ftpaGkY/0gTQCVzOWEHaDTc8eluySTIBcMlrnoj A7bpq/jGWCKrGWEG4i/f9QPw+etdnmi6aNApV/eEAW3Tzm3YzmZLZA+pSuoNNlvJoEv3 NSgVPHIyzyHslvql6NLII0rcSxqP7rcdxAUzq6c1M7wW5fQjBox8xn5lN1FSFjqkzziD ut1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :organization:references:in-reply-to:date:cc:to:from:subject :message-id; bh=+d+FvgHzo8NAygDB5xy4zk+j9L/tCprLk+O5Qo4uRdM=; b=JXG/o6qHIm6Acz5ZSPuZnzYpTr+uHwq9Zb5PRj1fN2RjZ2RAqGusLaxTgLZaRrjTVw b3SqO6nGwQDK5aq+MgarAgbSeV9VywTs+ZQ9SI2mfe4uLC52t+8l+2hilxFzCN0W/J9K 2dHwgPwR+13dbqzWeVxZSNG66f9EgcwCqVxhZaZgHPlh4MDLf+tQWEdA5u9zIa1mrEpw IWJTouKnzJpuGvM6dHmFozOJ91i4EWDH5mY2TLRDmfpeCKsOkG0MDnlrKgVxQh3ovL7R plMO6dmSHHazNEwi4M/BRj3nygmhSugcu8838eVJOkHMKXenulHF9yX43Xi+CH9O9rZ8 ASgA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e4si7703855pfe.4.2019.03.17.10.49.48; Sun, 17 Mar 2019 10:50:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727236AbfCQRr7 (ORCPT + 99 others); Sun, 17 Mar 2019 13:47:59 -0400 Received: from hermes.aosc.io ([199.195.250.187]:51214 "EHLO hermes.aosc.io" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726115AbfCQRr7 (ORCPT ); Sun, 17 Mar 2019 13:47:59 -0400 X-Greylist: delayed 484 seconds by postgrey-1.27 at vger.kernel.org; Sun, 17 Mar 2019 13:47:58 EDT Received: from localhost (localhost [127.0.0.1]) (Authenticated sender: icenowy@aosc.io) by hermes.aosc.io (Postfix) with ESMTPSA id E76DDA542E; Sun, 17 Mar 2019 17:39:49 +0000 (UTC) Message-ID: <2485e6c52810df376a0df6eb7f749f35b7b19044.camel@aosc.xyz> Subject: Re: [PATCH 0/7] Timer & SPI support for Allwinner suniv F1C100s From: Icenowy Zheng To: Daniel Lezcano , Thomas Gleixner , Mesih Kilinc , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Maxime Ripard , Chen-Yu Tsai , Linus Walleij , Rob Herring Date: Mon, 18 Mar 2019 01:39:44 +0800 In-Reply-To: References: Organization: Anthon Open-Source Community Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 在 2019-02-11一的 12:21 +0300,Mesih Kilinc写道: > This is followup series for F1C100s initial support patchset. > All patches merged except patch 1 ~ 2 which is related to timer. > I am resending those since they are already have Acked tags. Ping. Could you please merge these timer-related patches? Thanks! Icenowy > > Our dt-bindings for F1C100s are merged, we can now use them at our > device tree source - patch 3. > > Also this series add spi support and enables spi flash at Lichee-pi > Nano > in patch 4 ~ 7. This patches are based on Icenowy's work. > > Thanks! > > Mesih Kilinc (7): > dt-bindings: timer: Add Allwinner suniv timer > clocksource: sun4i: add a compatible for suniv > ARM: dts: suniv: Add dt-binding headers for F1C100s > dt-bindings: spi: Add Support for Allwinner F1C100s > ARM: dts: suniv: Add SPI device-tree nodes > ARM: dts: suniv: Add pinmux for SPI0 and SPI1 of F1C100s > ARM: dts: f1c100s: Activate SPI flash on Lichee Pi Nano > > .../devicetree/bindings/spi/spi-sun6i.txt | 5 +- > .../bindings/timer/allwinner,sun4i-timer.txt | 4 +- > arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts | 13 ++++++ > arch/arm/boot/dts/suniv-f1c100s.dtsi | 53 > +++++++++++++++++++--- > drivers/clocksource/timer-sun4i.c | 5 +- > 5 files changed, 70 insertions(+), 10 deletions(-) >