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Subject: Re: [PATCH v3 5/8] phy: amlogic: add Amlogic G12A USB2 PHY Driver
To:     Neil Armstrong <narmstrong@baylibre.com>,
        <gregkh@linuxfoundation.org>, <hminas@synopsys.com>,
        <balbi@kernel.org>
CC:     <linux-amlogic@lists.infradead.org>, <linux-usb@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>,
        Martin Blumenstingl <martin.blumenstingl@googlemail.com>
References: <20190318101153.7531-1-narmstrong@baylibre.com>
 <20190318101153.7531-6-narmstrong@baylibre.com>
From:   Kishon Vijay Abraham I <kishon@ti.com>
Message-ID: <a0001535-350a-6f3b-a8f4-3b853e4bc990@ti.com>
Date:   Mon, 18 Mar 2019 15:48:52 +0530
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Hi,

On 18/03/19 3:41 PM, Neil Armstrong wrote:
> This adds support for the USB2 PHY found in the Amlogic G12A SoC Family.
> 
> It supports Host and/or Peripheral mode, depending on it's position.
> The first PHY is only used as Host, but the second supports Dual modes
> defined by the USB Control Glue HW in front of the USB Controllers.
> 
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
>  drivers/phy/amlogic/Kconfig               |  11 ++
>  drivers/phy/amlogic/Makefile              |   1 +
>  drivers/phy/amlogic/phy-meson-g12a-usb2.c | 189 ++++++++++++++++++++++
>  3 files changed, 201 insertions(+)
>  create mode 100644 drivers/phy/amlogic/phy-meson-g12a-usb2.c
> 
> diff --git a/drivers/phy/amlogic/Kconfig b/drivers/phy/amlogic/Kconfig
> index 23fe1cda2f70..560ff0f1ed4c 100644
> --- a/drivers/phy/amlogic/Kconfig
> +++ b/drivers/phy/amlogic/Kconfig
> @@ -36,3 +36,14 @@ config PHY_MESON_GXL_USB3
>  	  Enable this to support the Meson USB3 PHY and OTG detection
>  	  IP block found in Meson GXL and GXM SoCs.
>  	  If unsure, say N.
> +
> +config PHY_MESON_G12A_USB2
> +	tristate "Meson G12A USB2 PHY driver"
> +	default ARCH_MESON
> +	depends on OF && (ARCH_MESON || COMPILE_TEST)
> +	select GENERIC_PHY
> +	select REGMAP_MMIO
> +	help
> +	  Enable this to support the Meson USB2 PHYs found in Meson
> +	  G12A SoCs.
> +	  If unsure, say N.
> diff --git a/drivers/phy/amlogic/Makefile b/drivers/phy/amlogic/Makefile
> index 4fd8848c194d..7d4d10f5a6b3 100644
> --- a/drivers/phy/amlogic/Makefile
> +++ b/drivers/phy/amlogic/Makefile
> @@ -1,3 +1,4 @@
>  obj-$(CONFIG_PHY_MESON8B_USB2)		+= phy-meson8b-usb2.o
>  obj-$(CONFIG_PHY_MESON_GXL_USB2)	+= phy-meson-gxl-usb2.o
> +obj-$(CONFIG_PHY_MESON_G12A_USB2)	+= phy-meson-g12a-usb2.o
>  obj-$(CONFIG_PHY_MESON_GXL_USB3)	+= phy-meson-gxl-usb3.o
> diff --git a/drivers/phy/amlogic/phy-meson-g12a-usb2.c b/drivers/phy/amlogic/phy-meson-g12a-usb2.c
> new file mode 100644
> index 000000000000..9f35259f237f
> --- /dev/null
> +++ b/drivers/phy/amlogic/phy-meson-g12a-usb2.c
> @@ -0,0 +1,189 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Meson G12A USB2 PHY driver
> + *
> + * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> + * Copyright (C) 2017 Amlogic, Inc. All rights reserved
> + * Copyright (C) 2019 BayLibre, SAS
> + * Author: Neil Armstrong <narmstrong@baylibre.com>
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/regmap.h>
> +#include <linux/reset.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +
> +#define PHY_CTRL_R0						0x0
> +#define PHY_CTRL_R1						0x4
> +#define PHY_CTRL_R2						0x8
> +#define PHY_CTRL_R3						0xc
> +#define PHY_CTRL_R4						0x10
> +#define PHY_CTRL_R5						0x14
> +#define PHY_CTRL_R6						0x18
> +#define PHY_CTRL_R7						0x1c
> +#define PHY_CTRL_R8						0x20
> +#define PHY_CTRL_R9						0x24
> +#define PHY_CTRL_R10						0x28
> +#define PHY_CTRL_R11						0x2c
> +#define PHY_CTRL_R12						0x30
> +#define PHY_CTRL_R13						0x34
> +#define PHY_CTRL_R14						0x38
> +#define PHY_CTRL_R15						0x3c
> +#define PHY_CTRL_R16						0x40
> +#define PHY_CTRL_R17						0x44
> +#define PHY_CTRL_R18						0x48
> +#define PHY_CTRL_R19						0x4c
> +#define PHY_CTRL_R20						0x50
> +#define PHY_CTRL_R21						0x54
> +#define PHY_CTRL_R22						0x58
> +#define PHY_CTRL_R23						0x5c
> +
> +#define RESET_COMPLETE_TIME					1000
> +#define PLL_RESET_COMPLETE_TIME					100
> +
> +struct phy_meson_g12a_usb2_priv {
> +	struct device		*dev;
> +	struct regmap		*regmap;
> +	struct clk		*clk;
> +	struct reset_control	*reset;
> +};
> +
> +static const struct regmap_config phy_meson_g12a_usb2_regmap_conf = {
> +	.reg_bits = 8,
> +	.val_bits = 32,
> +	.reg_stride = 4,
> +	.max_register = PHY_CTRL_R23,
> +};
> +
> +static int phy_meson_g12a_usb2_init(struct phy *phy)
> +{
> +	struct phy_meson_g12a_usb2_priv *priv = phy_get_drvdata(phy);
> +	int ret;
> +
> +	ret = reset_control_reset(priv->reset);
> +	if (ret)
> +		return ret;
> +
> +	udelay(RESET_COMPLETE_TIME);
> +
> +	/* usb2_otg_aca_en == 0 */
> +	regmap_update_bits(priv->regmap, PHY_CTRL_R21, BIT(2), 0);
> +
> +	/* PLL Setup : 24MHz * 20 / 1 = 480MHz */
> +	regmap_write(priv->regmap, PHY_CTRL_R16, 0x39400414);
> +	regmap_write(priv->regmap, PHY_CTRL_R17, 0x927e0000);
> +	regmap_write(priv->regmap, PHY_CTRL_R18, 0xac5f49e5);

Please add macros for each of the individual bit-fields.
> +
> +	udelay(PLL_RESET_COMPLETE_TIME);
> +
> +	/* UnReset PLL */
> +	regmap_write(priv->regmap, PHY_CTRL_R16, 0x19400414);

Here too..

Thanks
Kishon