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[209.132.180.67]) by mx.google.com with ESMTP id j71si10390609pfc.280.2019.03.18.12.43.03; Mon, 18 Mar 2019 12:43:19 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@googlemail.com header.s=20161025 header.b=lQE2W46i; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=googlemail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727570AbfCRTlv (ORCPT + 99 others); Mon, 18 Mar 2019 15:41:51 -0400 Received: from mail-oi1-f193.google.com ([209.85.167.193]:34838 "EHLO mail-oi1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727548AbfCRTlu (ORCPT ); Mon, 18 Mar 2019 15:41:50 -0400 Received: by mail-oi1-f193.google.com with SMTP id j132so11076533oib.2; Mon, 18 Mar 2019 12:41:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=M139LBtlkNrQR6u9V/xwOU9GjCtoAeXlSSkK8+ntcTE=; b=lQE2W46iJf0QnJmPvkcAeS0bcn8HU/eQoU1uYCSye2F1xkagCnvS/qmLd1nUPmUjx1 f28ns82LbDnNl8T/l/tw/UbWhHr0oSQpfTGjFm5CZvUWt9mkvpYIvFSDsxPBO8ug82jl 4f9+C7uMOawkm4xGdgyjgDF8ZAUlA+vRRpGPz52n7+/CbmWQPCEJvnaxsA7MbfpeuHFk 2+mDVMA6ugFYOGrxcF0jWmKz5h2MkD4Nif1zdoB79reTVDvfIEGYnCCP45M+rySGSvXI qAMOH7V6imNTVxhjJj9vHtin+jMWEVeh/Z90FcxfIY8GbTA8Q2GA7L2rcJktZ8uVn/Kd Uh3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=M139LBtlkNrQR6u9V/xwOU9GjCtoAeXlSSkK8+ntcTE=; b=iTIKb8wqzGNtSaa7tR+IBy8txkecgCKUgR9fJSD1xDQsqjRHcv4+MBkr+pgR4X80Zx G5/0mBmPG8frvmelJof077HAXe865aisxpn8hKJGwGkbgkPGx6BwYrE4FQ+fQ2ndoKg5 XXiSDwQGtZn/kAfb6HgZgI5CYDtJNiIPnvwo/ezwIMwvgs42nubcYTKXdYNAUTwAXF7s ZAqUuX2st9eCoNzFO4krhbwjvYJCGn3GuWFkjIwreFWxxZsoeS1vw529XHnzO+J30fDG /d+LOVf3PC1mo7VVspLJIFy3SfolFo85rvnq4eimqnKAWGXcVtKTLN2kFmrA03F8bQrT JdYw== X-Gm-Message-State: APjAAAUccM/JNe2UcEwiGtb/GyQRUztSvk+zOzv9lYFAfhkfMB0o9Bwi CVL548BREDF4RsRiISOEu+sZY8OFoUGuL1W6KyA= X-Received: by 2002:aca:a9ce:: with SMTP id s197mr361423oie.129.1552938108945; Mon, 18 Mar 2019 12:41:48 -0700 (PDT) MIME-Version: 1.0 References: <20190318101153.7531-1-narmstrong@baylibre.com> In-Reply-To: From: Martin Blumenstingl Date: Mon, 18 Mar 2019 20:41:38 +0100 Message-ID: Subject: Re: [PATCH v3 0/8] arm64: meson: Add support for USB on Amlogic G12A To: Neil Armstrong Cc: gregkh@linuxfoundation.org, hminas@synopsys.com, balbi@kernel.org, kishon@ti.com, linux-amlogic@lists.infradead.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Neil, On Mon, Mar 18, 2019 at 2:29 PM Neil Armstrong wrote: > > On 18/03/2019 11:11, Neil Armstrong wrote: > > This patchset adds support for USB on Amlogic G12A SoCs. > > > > This patchset is composed with : > > - bindings of the PHYs > > - bindings of the USB Control Glue > > - PHY Drivers > > - USB Control Glue driver > > > > Device Tree nodes will be added in a separate patchset. > > > > The Amlogic G12A USB Complex is composed of : > > - 2 USB Controllers : > > * DWC3 for USB2 and USB3 Host functionality > > * DWC2 for USB2 Peripheral functionality > > - 2 USB2 OTG PHYs, only a single one will be routed to either DWC2 to DWC3 > > - 1 USB3 PHY shared with PCIE funcionnality > > - A Glue to control PHY routing, setup and OTG detection > > > > The Glue configures the UTMI 8bit interfaces for the USB2 PHYs, including > > routing of the OTG PHY between the DWC3 and DWC2 controllers, and > > setups the on-chip OTG mode selection for this PHY. > > > > This drivers supports the on-probe setup of the OTG mode, and manually > > via the USB Role interface. The IRQ mode change detect is yet to be added > > in a future patchset, mainly due to lack of hardware to validate on. > > > > Resent with USB2 PHY registers documented awesome, thank you very much for this! Regards Martin