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Date:   Tue, 19 Mar 2019 11:35:48 +0000
From:   Marc Zyngier <marc.zyngier@arm.com>
To:     Kishon Vijay Abraham I <kishon@ti.com>
Cc:     Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
        Murali Karicheri <m-karicheri2@ti.com>,
        Bjorn Helgaas <bhelgaas@google.com>,
        Jingoo Han <jingoohan1@gmail.com>,
        Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
        <linux-pci@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v4 3/9] PCI: keystone: Convert to using hierarchy domain
 for legacy interrupts
Message-ID: <20190319113548.2a5b77a7@why.wild-wind.fr.eu.org>
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On Tue, 19 Mar 2019 16:22:39 +0530
Kishon Vijay Abraham I <kishon@ti.com> wrote:

Hi Kishon,

> Hi Marc,
> 
> On 18/03/19 4:46 PM, Marc Zyngier wrote:
> > On Mon, 18 Mar 2019 11:03:07 +0530
> > Kishon Vijay Abraham I <kishon@ti.com> wrote:
> >   
> >> Hi Marc,
> >>
> >> On 07/03/19 5:32 PM, Marc Zyngier wrote:  
> >>> On Thu, 07 Mar 2019 09:12:30 +0000,
> >>> Kishon Vijay Abraham I <kishon@ti.com> wrote:    


[...]

> >>>> It is pulse triggered at subsystem level. Quoting the TRM
> >>>> "The interrupt request signal at the PCIe SS boundary is a pulse signal that is
> >>>> triggered each time an assert interrupt message is received." The PCIe
> >>>> subsystem also has a level signal (interrupt pending signal) but the interrupt
> >>>> request signal is the one that is connected to GIC.    
> >>>
> >>> This looks completely wrong. MSIs are always edge, and legacy always
> >>> level, end of story. If your HW is any different, then it doesn't seem
> >>> to be compliant with PCI.    
> >>
> >> Agree that Legacy interrupts ought to be level-triggered. I checked this with
> >> HW team and I've copy-pasted the response.
> >>
> >> "The legacy interrupts from the PCIe controller are still level. The PCIe
> >> controller will hold the legacy interrupt lines high until a de-assert message
> >> is sent back. The pulse interrupt is only to send the interrupt from the PCIe
> >> sub-system to the SoC interrupt controller. This should not impact the
> >> operation of the legacy interrupt on the PCIe side."
> >>
> >> Looks like the interrupts are propagated multiple levels and only the last
> >> level to the interrupt controller is pulse.  
> > 
> > Let's take an example: My device (let's assume a network controller of
> > some sort) generates an interrupt. Level is high, and you observe an
> > edge. The driver handles the interrupt, but due to a race, the line
> > stays high (the device has received a new packet).
> > 
> > How is a *new* edge generated? The line never transited to low, and we
> > have more packet to process. With a level triggered interrupt, you just
> > take the interrupt again. With an edge interrupt, you need to actively
> > resample the level and retrigger the interrupt. How is this done?  
> 
> There might be an actual issue in the HW while converting from level to edge
> where new edge interrupt might not be generated in the case you just mentioned.
> I am checking this with HW folks.

There is (non-PCI) HW that does that. On EOI, they force the interrupt
controller to resample the level, which results in a new edge to be
generated if the level is high. This of course require some HW, usually
a register taking the ID of the line that needs resampling. I'd be
surprised if there wasn't something along those lines in your HW, at
least as a debug mechanism.

> Since this might take time, I'll remove this patch and resend only the MSI
> cleanup in order to make progress.

OK.

Thanks,

	M.
-- 
Without deviation from the norm, progress is not possible.