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Tue, 19 Mar 2019 12:04:36 +0000 Envelope-to: arnd@arndb.de, gregkh@linuxfoundation.org, michal.simek@xilinx.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dragan.cvetic@xilinx.com, derek.kiernan@xilinx.com Received: from [149.199.110.15] (port=43674 helo=xirdraganc40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1h6DTw-0003Ch-4i; Tue, 19 Mar 2019 12:04:36 +0000 From: Dragan Cvetic To: , , , CC: , Dragan Cvetic , Derek Kiernan Subject: [PATCH 06/12] misc: xilinx_sdfec: Add ability to configure turbo mode Date: Tue, 19 Mar 2019 12:04:18 +0000 Message-ID: <1552997064-432700-7-git-send-email-dragan.cvetic@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1552997064-432700-1-git-send-email-dragan.cvetic@xilinx.com> References: <1552997064-432700-1-git-send-email-dragan.cvetic@xilinx.com> MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.80.198;IPV:CAL;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(136003)(346002)(39860400002)(396003)(376002)(2980300002)(199004)(189003)(7636002)(76176011)(356004)(26005)(28376004)(305945005)(93146003)(2906002)(50226002)(36756003)(110136005)(316002)(47776003)(4326008)(5660300002)(60926002)(71366001)(9786002)(48376002)(50466002)(107886003)(54906003)(8676002)(26826003)(8746002)(8936002)(478600001)(246002)(36906005)(106466001)(6666004)(336012)(106002)(44832011)(5024004)(14444005)(2201001)(186003)(956004)(2616005)(446003)(51416003)(11346002)(426003)(126002)(7696005)(476003)(486006)(102446001)(461764006);DIR:OUT;SFP:1101;SCL:1;SRVR:DM6PR02MB5915;H:xir-pvapexch02.xlnx.xilinx.com;FPR:;SPF:Pass;LANG:en;PTR:unknown-80-198.xilinx.com;A:1;MX:1; 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Reviewed-by: Michal Simek Tested-by: Dragan Cvetic Signed-off-by: Derek Kiernan Signed-off-by: Dragan Cvetic --- drivers/misc/xilinx_sdfec.c | 83 ++++++++++++++++++++++++++++++++++++= ++++ include/uapi/misc/xilinx_sdfec.h | 71 ++++++++++++++++++++++++++++++++++ 2 files changed, 154 insertions(+) diff --git a/drivers/misc/xilinx_sdfec.c b/drivers/misc/xilinx_sdfec.c index d9ead0b..58b1c57 100644 --- a/drivers/misc/xilinx_sdfec.c +++ b/drivers/misc/xilinx_sdfec.c @@ -115,6 +115,12 @@ static dev_t xsdfec_devt; /* BYPASS Register */ #define XSDFEC_BYPASS_ADDR (0x3C) +/* Turbo Code Register */ +#define XSDFEC_TURBO_ADDR (0x100) +#define XSDFEC_TURBO_SCALE_MASK (0xFFF) +#define XSDFEC_TURBO_SCALE_BIT_POS (8) +#define XSDFEC_TURBO_SCALE_MAX (15) + /** * struct xsdfec_clks - For managing SD-FEC clocks * @core_clk: Main processing clock for core @@ -251,6 +257,77 @@ static int xsdfec_dev_release(struct inode *iptr, stru= ct file *fptr) return 0; } +static int xsdfec_set_turbo(struct xsdfec_dev *xsdfec, void __user *arg) +{ + struct xsdfec_turbo turbo; + int err; + u32 turbo_write; + + err =3D copy_from_user(&turbo, arg, sizeof(turbo)); + if (err) { + dev_err(xsdfec->dev, "%s failed for SDFEC%d", __func__, + xsdfec->config.fec_id); + return -EFAULT; + } + + if (turbo.alg >=3D XSDFEC_TURBO_ALG_MAX) { + dev_err(xsdfec->dev, + "%s invalid turbo alg value %d for SDFEC%d", __func= __, + turbo.alg, xsdfec->config.fec_id); + return -EINVAL; + } + + if (turbo.scale > XSDFEC_TURBO_SCALE_MAX) { + dev_err(xsdfec->dev, + "%s invalid turbo scale value %d for SDFEC%d", __fu= nc__, + turbo.scale, xsdfec->config.fec_id); + return -EINVAL; + } + + /* Check to see what device tree says about the FEC codes */ + if (xsdfec->config.code =3D=3D XSDFEC_LDPC_CODE) { + dev_err(xsdfec->dev, + "%s: Unable to write Turbo to SDFEC%d check DT", + __func__, xsdfec->config.fec_id); + return -EIO; + } + + turbo_write =3D ((turbo.scale & XSDFEC_TURBO_SCALE_MASK) + << XSDFEC_TURBO_SCALE_BIT_POS) | + turbo.alg; + xsdfec_regwrite(xsdfec, XSDFEC_TURBO_ADDR, turbo_write); + return err; +} + +static int xsdfec_get_turbo(struct xsdfec_dev *xsdfec, void __user *arg) +{ + u32 reg_value; + struct xsdfec_turbo turbo_params; + int err; + + if (xsdfec->config.code =3D=3D XSDFEC_LDPC_CODE) { + dev_err(xsdfec->dev, + "%s: SDFEC%d is configured for LDPC, check DT", + __func__, xsdfec->config.fec_id); + return -EIO; + } + + reg_value =3D xsdfec_regread(xsdfec, XSDFEC_TURBO_ADDR); + + turbo_params.scale =3D (reg_value & XSDFEC_TURBO_SCALE_MASK) >> + XSDFEC_TURBO_SCALE_BIT_POS; + turbo_params.alg =3D reg_value & 0x1; + + err =3D copy_to_user(arg, &turbo_params, sizeof(turbo_params)); + if (err) { + dev_err(xsdfec->dev, "%s failed for SDFEC%d", __func__, + xsdfec->config.fec_id); + err =3D -EFAULT; + } + + return err; +} + static u32 xsdfec_translate_axis_width_cfg_val(enum xsdfec_axis_width axis_width_cfg) { @@ -352,6 +429,12 @@ static long xsdfec_dev_ioctl(struct file *fptr, unsign= ed int cmd, } switch (cmd) { + case XSDFEC_SET_TURBO: + rval =3D xsdfec_set_turbo(xsdfec, arg); + break; + case XSDFEC_GET_TURBO: + rval =3D xsdfec_get_turbo(xsdfec, arg); + break; default: /* Should not get here */ dev_err(xsdfec->dev, "Undefined SDFEC IOCTL"); diff --git a/include/uapi/misc/xilinx_sdfec.h b/include/uapi/misc/xilinx_sd= fec.h index 0497b66..1a15771 100644 --- a/include/uapi/misc/xilinx_sdfec.h +++ b/include/uapi/misc/xilinx_sdfec.h @@ -39,6 +39,22 @@ enum xsdfec_order { }; /** + * enum xsdfec_turbo_alg - Turbo Algorithm Type. + * @XSDFEC_MAX_SCALE: Max Log-Map algorithm with extrinsic scaling. When + * scaling is set to this is equivalent to the Max Log-M= ap + * algorithm. + * @XSDFEC_MAX_STAR: Log-Map algorithm. + * @XSDFEC_TURBO_ALG_MAX: Used to indicate out of bound Turbo algorithms. + * + * This enum specifies which Turbo Decode algorithm is in use. + */ +enum xsdfec_turbo_alg { + XSDFEC_MAX_SCALE =3D 0, + XSDFEC_MAX_STAR, + XSDFEC_TURBO_ALG_MAX, +}; + +/** * enum xsdfec_state - State. * @XSDFEC_INIT: Driver is initialized. * @XSDFEC_STARTED: Driver is started. @@ -96,6 +112,33 @@ enum xsdfec_axis_word_include { }; /** + * struct xsdfec_turbo - User data for Turbo codes. + * @alg: Specifies which Turbo decode algorithm to use + * @scale: Specifies the extrinsic scaling to apply when the Max Scale alg= orithm + * has been selected + * + * Turbo code structure to communicate parameters to XSDFEC driver. + */ +struct xsdfec_turbo { + enum xsdfec_turbo_alg alg; + u8 scale; +}; + +/** + * struct xsdfec_status - Status of SD-FEC core. + * @fec_id: ID of SD-FEC instance. ID is limited to the number of active + * SD-FEC's in the FPGA and is related to the driver instance + * Minor number. + * @state: State of the SD-FEC core + * @activity: Describes if the SD-FEC instance is Active + */ +struct xsdfec_status { + s32 fec_id; + enum xsdfec_state state; + char activity; +}; + +/** * struct xsdfec_irq - Enabling or Disabling Interrupts. * @enable_isr: If true enables the ISR * @enable_ecc_isr: If true enables the ECC ISR @@ -137,4 +180,32 @@ struct xsdfec_config { * XSDFEC IOCTL List */ #define XSDFEC_MAGIC 'f' +/** + * DOC: XSDFEC_SET_TURBO + * @Parameters + * + * @struct xsdfec_turbo * + * Pointer to the &struct xsdfec_turbo that contains the Turbo decode + * settings for the SD-FEC core + * + * @Description + * + * ioctl that sets the SD-FEC Turbo parameter values + * + * This can only be used when the driver is in the XSDFEC_STOPPED state + */ +#define XSDFEC_SET_TURBO _IOW(XSDFEC_MAGIC, 4, struct xsdfec_turbo *) +/** + * DOC: XSDFEC_GET_TURBO + * @Parameters + * + * @struct xsdfec_turbo * + * Pointer to the &struct xsdfec_turbo that contains the current Turbo + * decode settings of the SD-FEC Block + * + * @Description + * + * ioctl that returns SD-FEC turbo param values + */ +#define XSDFEC_GET_TURBO _IOR(XSDFEC_MAGIC, 7, struct xsdfec_turbo *) #endif /* __XILINX_SDFEC_H__ */ -- 2.7.4 This email and any attachments are intended for the sole use of the named r= ecipient(s) and contain(s) confidential information that may be proprietary= , privileged or copyrighted under applicable law. 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