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[209.132.180.67]) by mx.google.com with ESMTP id k18si18581pfi.224.2019.03.19.15.08.46; Tue, 19 Mar 2019 15:09:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@agner.ch header.s=dkim header.b=lfY4eMt8; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727522AbfCSWHj (ORCPT + 99 others); Tue, 19 Mar 2019 18:07:39 -0400 Received: from mail.kmu-office.ch ([178.209.48.109]:58928 "EHLO mail.kmu-office.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727384AbfCSWHj (ORCPT ); Tue, 19 Mar 2019 18:07:39 -0400 Received: from webmail.kmu-office.ch (unknown [IPv6:2a02:418:6a02::a3]) by mail.kmu-office.ch (Postfix) with ESMTPSA id DEAA35C01C4; Tue, 19 Mar 2019 23:07:35 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=agner.ch; s=dkim; t=1553033255; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Zku767815alubGZKI3FUMQcNR5dleh8JfwJ33Armyzk=; b=lfY4eMt8md6/REwdfSzw09Eydi/qfPF6O4aMs/lFxfmlWJI5MN9MgxvbTMCyGhmH4Nd5Nr 0C+brQcaoJfYIcgoZkyZAEWwvhBrQ4E4gfo2OYv8M6AUuE1TJVtHuOx6+HoZz3EsNjkDlt d/VY79xHwubznS4I7aXuLQsxXOOmqL4= MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Date: Tue, 19 Mar 2019 23:07:35 +0100 From: Stefan Agner To: Nick Desaulniers Cc: Russell King , Robin Murphy , Will Deacon , Nathan Chancellor , Arnd Bergmann , Ard Biesheuvel , Nicolas Pitre , Thierry Reding , julien.thierry@arm.com, Mark Rutland , LKML , Linux ARM Subject: Re: [PATCH v2 1/2] ARM: drop WASM to work around LLVM issue In-Reply-To: References: Message-ID: X-Sender: stefan@agner.ch User-Agent: Roundcube Webmail/1.3.7 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 18.03.2019 19:09, Nick Desaulniers wrote: > On Sun, Mar 17, 2019 at 4:05 PM Stefan Agner wrote: >> >> Currently LLVM's integrated assembler does not recognize .w form >> of the pld instructions (LLVM Bug 40972 [0]): >> >> ./arch/arm/include/asm/processor.h:133:5: error: invalid instruction >> "pldw.w\t%a0 \n" >> ^ >> :2:1: note: instantiated into assembly here >> pldw.w [r0] >> ^ >> 1 error generated. >> >> The W macro for generating wide instructions when targeting Thumb-2 >> is not strictly required for the preload data instructions (pld, pldw) >> since they are only available as wide instructions. The GNU assembler >> works with or without the .w appended when compiling an Thumb-2 kernel. >> >> Drop the macro to work around LLVM Bug 40972 issue. >> >> [0] https://bugs.llvm.org/show_bug.cgi?id=40972 >> >> Signed-off-by: Stefan Agner > > Thanks for the bug report and patch. > Reviewed-by: Nick Desaulniers > > Just curious, there are only 3 other expansion sites of this macro. > Are any of those problematic? Looks like nop.w, sev.w and b.w? > All three sites are in inline assembly, and I did a bunch of successful Thumb2 builds using the integrated assembler, so I think all those sites have been assembled by LLVM successfully. Also confirmed those three instructions with the reproducer example from the LLVM bug above. -- Stefan >> --- >> Changes in v2: >> - Reword commit message to reflect the fact that this is a work around >> for LLVM. >> >> arch/arm/include/asm/processor.h | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h >> index 57fe73ea0f72..5d06f75ffad4 100644 >> --- a/arch/arm/include/asm/processor.h >> +++ b/arch/arm/include/asm/processor.h >> @@ -135,8 +135,8 @@ static inline void prefetchw(const void *ptr) >> __asm__ __volatile__( >> ".arch_extension mp\n" >> __ALT_SMP_ASM( >> - WASM(pldw) "\t%a0", >> - WASM(pld) "\t%a0" >> + "pldw\t%a0", >> + "pld\t%a0" >> ) >> :: "p" (ptr)); >> } >> -- >> 2.21.0 >>