Received: by 2002:ac0:bc90:0:0:0:0:0 with SMTP id a16csp577770img; Wed, 20 Mar 2019 06:45:29 -0700 (PDT) X-Google-Smtp-Source: APXvYqwj4j3TL/5fD5n1iorLhC+2ZbnQdveL6s+yrxbg7b9bXSFv1L7HmZ0+2O385IhM/iAxDWvO X-Received: by 2002:a17:902:1a9:: with SMTP id b38mr8517819plb.37.1553089529664; Wed, 20 Mar 2019 06:45:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553089529; cv=none; d=google.com; s=arc-20160816; b=0joQHqADH0SzuCEt8KSAfM1gusHfRj7r6t7sdFApgEKjRglsUBjLMeDIM+Go+787Zt ya3hGp20rZ8ZdbKi/ysSDzenv2NMLJKPuXQwRx2xB7jnDdhdElVASDjtfnAXZVhfK1qe +MzNb4i0kJBlJ6DMmKs/q3hSlJlKeBwOvT9k+LJ3MisweNrlRPl7atdhhmyVyE7W+PH4 q1hWxOmfmZwKVA6Ed6HXirGdxn9m5wnwyZ8jbqvlIxol0B/KC+4eQbAMzTOeTkT6UXRP Gi6ezqkxA56x8Zfypv8ef9xCtI2IsX8+J2WrovejD1FcpexMxSDh2YNQRNzS3Bkh0TtF 05dw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:user-agent:in-reply-to :content-disposition:mime-version:references:message-id:subject:cc :to:from:date:dkim-signature; bh=SYYt5Wqq9VnWAJOdSwLRWHVsIVJz75AKS4JXDaBdyy4=; b=m4UhQZZQtEYgwiSlMNJIZhlw10oc+MWeeGLtwOJIWSDc85Awfe6RHmKeNzzDC2erjr ecI9lsalMSPe9co7Lb105RAHI0DZCgT2Yy5X1Vptl6LvxWSOEKgX/deE/b7NVin7Mnwr 94rqh0OlldjbtL4HCdk8XMpJ1PLEICcuG8PWx0cXHCC9q7kVf4yu19/z12IBuctgfaUk FVvB5aWUxvTd3IqAUqvSaj6cgE6obku0hl7xSVyUGrsDbFEp9Sc346FyN7Vvgjeqkxgf 0bu2ZXgh0rXy3CyCtONY0qXciGLrVR0i+32Jxjb1Vkx5TBZNSakydN6HOMO1vsBWBw+p PfUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=e5V1wNCf; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k17si1095039pfk.40.2019.03.20.06.45.13; Wed, 20 Mar 2019 06:45:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=e5V1wNCf; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728084AbfCTNoH (ORCPT + 99 others); Wed, 20 Mar 2019 09:44:07 -0400 Received: from mail-pg1-f195.google.com ([209.85.215.195]:42230 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725905AbfCTNoH (ORCPT ); Wed, 20 Mar 2019 09:44:07 -0400 Received: by mail-pg1-f195.google.com with SMTP id p6so1835520pgh.9; Wed, 20 Mar 2019 06:44:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=SYYt5Wqq9VnWAJOdSwLRWHVsIVJz75AKS4JXDaBdyy4=; b=e5V1wNCf+7iV/YnXQvNVYbGOih8jfwh0l0ZpXVtlwcmI5o16YPvKl/pJCcfP6iTqOm ke5srHq14TvWfiw1jpeJiHOacnM49Qdity7piUjvh2ccP5h0xD7SCHiDVC12p3bgKiGC BbHO2GH/NTT1onAHhMzfPZwkFxvb8ytxk80wG+njxEWBm58lwURjo/9Z+iDh4uAhCatO OuuIRwZWpb1n+6hO8FmGuuJSKc6Uz5dpGqB7D68GHh1DbY6B5vz85J4SifjEft7yqWvT MHXPfawTpTgPKL1RkObVqQ15xzcvRcJzS8z90H2IYdv643fMGB5Z/7SbR6dGwb5cK3UL uDtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:date:from:to:cc:subject:message-id :references:mime-version:content-disposition:in-reply-to:user-agent; bh=SYYt5Wqq9VnWAJOdSwLRWHVsIVJz75AKS4JXDaBdyy4=; b=UsizIZ81P1ptlMywGOU6VI4N++hYmamCDgFG2fdtmTYkNN4CRlH7/ffgHE18tEUwRs yGBPq1FGRf621O5HEBeqdKYX8yAVpKMlsaOtvcJfQPbMZaslxgSar7EUU7C/7sDDUVrA Dzfg050ntZmQhvnJAlKhKT6r04gdIyyyYtFy4+gCUJ5mc7Txumr3Fd4V14XeJtGmmpfc It1BB0yXs9xgZzk3auy0oESX27Az//fcRlGLRe0KSixIcE5Op8XmaF7M8b8JRP1NU6qA lTZW6a3mcvLBQCBubQ2mhHpxTCYAno3UJBEunSbV155uCoTylZln1qHlm7fkvtY1QD5O n2wg== X-Gm-Message-State: APjAAAW98ZZiLSTAUIsw35pZl9DqHbu7ZAQIV9/qEX0NVjIL+X4seUt4 TDnOQD/5lO90OosyR2QtBe4= X-Received: by 2002:a65:52c8:: with SMTP id z8mr7919784pgp.259.1553089446201; Wed, 20 Mar 2019 06:44:06 -0700 (PDT) Received: from localhost ([2600:1700:e321:62f0:329c:23ff:fee3:9d7c]) by smtp.gmail.com with ESMTPSA id b8sm3415013pfi.129.2019.03.20.06.44.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 20 Mar 2019 06:44:05 -0700 (PDT) Date: Wed, 20 Mar 2019 06:44:04 -0700 From: Guenter Roeck To: Anson Huang Cc: "wim@linux-watchdog.org" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "kernel@pengutronix.de" , "festevam@gmail.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" , Aisheng Dong , Daniel Baluta , "heiko@sntech.de" , "horms+renesas@verge.net.au" , Andy Gross , "maxime.ripard@bootlin.com" , "olof@lixom.net" , "bjorn.andersson@linaro.org" , "jagan@amarulasolutions.com" , "enric.balletbo@collabora.com" , "ezequiel@collabora.com" , "stefan.wahren@i2se.com" , "marc.w.gonzalez@free.fr" , "linux-watchdog@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , dl-linux-imx Subject: Re: [PATCH V8 2/4] watchdog: imx_sc: Add i.MX system controller watchdog support Message-ID: <20190320134404.GA848@roeck-us.net> References: <1552630331-32068-1-git-send-email-Anson.Huang@nxp.com> <1552630331-32068-3-git-send-email-Anson.Huang@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1552630331-32068-3-git-send-email-Anson.Huang@nxp.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Mar 15, 2019 at 06:17:25AM +0000, Anson Huang wrote: > i.MX8QXP is an ARMv8 SoC which has a Cortex-M4 system controller > inside, the system controller is in charge of controlling power, > clock and watchdog etc.. > > This patch adds i.MX system controller watchdog driver support, > watchdog operation needs to be done in secure EL3 mode via > ARM-Trusted-Firmware, using SMC call, CPU will trap into > ARM-Trusted-Firmware and then it will request system controller > to do watchdog operation via IPC. > > Signed-off-by: Anson Huang Reviewed-by: Guenter Roeck Waiting for bindings approval, though. Plus a minor comment below. Guenter > --- > Changes since V7: > - remove the dependence of IMX_SCU as it does NOT call SCU API directly; > - add more detail info into the help section of how this module works; > - add back device id table since now we have watchdog node in DT. > --- > drivers/watchdog/Kconfig | 16 ++++ > drivers/watchdog/Makefile | 1 + > drivers/watchdog/imx_sc_wdt.c | 182 ++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 199 insertions(+) > create mode 100644 drivers/watchdog/imx_sc_wdt.c > > diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig > index 242eea8..44a3158 100644 > --- a/drivers/watchdog/Kconfig > +++ b/drivers/watchdog/Kconfig > @@ -641,6 +641,22 @@ config IMX2_WDT > To compile this driver as a module, choose M here: the > module will be called imx2_wdt. > > +config IMX_SC_WDT > + tristate "IMX SC Watchdog" > + depends on HAVE_ARM_SMCCC > + select WATCHDOG_CORE > + help > + This is the driver for the system controller watchdog > + on the NXP i.MX SoCs with system controller inside, the > + watchdog driver will call ARM SMC API and trap into > + ARM-Trusted-Firmware for operations, ARM-Trusted-Firmware > + will request system controller to execute the operations. > + If you have one of these processors and wish to have > + watchdog support enabled, say Y, otherwise say N. > + > + To compile this driver as a module, choose M here: the > + module will be called imx_sc_wdt. > + > config UX500_WATCHDOG > tristate "ST-Ericsson Ux500 watchdog" > depends on MFD_DB8500_PRCMU > diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile > index ba930e4..136d9f0 100644 > --- a/drivers/watchdog/Makefile > +++ b/drivers/watchdog/Makefile > @@ -68,6 +68,7 @@ obj-$(CONFIG_NUC900_WATCHDOG) += nuc900_wdt.o > obj-$(CONFIG_TS4800_WATCHDOG) += ts4800_wdt.o > obj-$(CONFIG_TS72XX_WATCHDOG) += ts72xx_wdt.o > obj-$(CONFIG_IMX2_WDT) += imx2_wdt.o > +obj-$(CONFIG_IMX_SC_WDT) += imx_sc_wdt.o > obj-$(CONFIG_UX500_WATCHDOG) += ux500_wdt.o > obj-$(CONFIG_RETU_WATCHDOG) += retu_wdt.o > obj-$(CONFIG_BCM2835_WDT) += bcm2835_wdt.o > diff --git a/drivers/watchdog/imx_sc_wdt.c b/drivers/watchdog/imx_sc_wdt.c > new file mode 100644 > index 0000000..c8a087a > --- /dev/null > +++ b/drivers/watchdog/imx_sc_wdt.c > @@ -0,0 +1,182 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright 2018-2019 NXP. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define DEFAULT_TIMEOUT 60 > +/* > + * Software timer tick implemented in scfw side, support 10ms to 0xffffffff ms > + * in theory, but for normal case, 1s~128s is enough, you can change this max > + * value in case it's not enough. > + */ > +#define MAX_TIMEOUT 128 > + > +#define IMX_SIP_TIMER 0xC2000002 > +#define IMX_SIP_TIMER_START_WDOG 0x01 > +#define IMX_SIP_TIMER_STOP_WDOG 0x02 > +#define IMX_SIP_TIMER_SET_WDOG_ACT 0x03 > +#define IMX_SIP_TIMER_PING_WDOG 0x04 > +#define IMX_SIP_TIMER_SET_TIMEOUT_WDOG 0x05 > +#define IMX_SIP_TIMER_GET_WDOG_STAT 0x06 > +#define IMX_SIP_TIMER_SET_PRETIME_WDOG 0x07 > + > +#define SC_TIMER_WDOG_ACTION_PARTITION 0 > + > +static bool nowayout = WATCHDOG_NOWAYOUT; > +module_param(nowayout, bool, 0000); > +MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" > + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); > + > +static unsigned int timeout = DEFAULT_TIMEOUT; I still don't understand why you explicitly disable configuring the watchdog timeout through devicetree (unless the user explicitly provides a timeout=0 module parameter). Maybe add some comment if you send another version. > +module_param(timeout, uint, 0000); > +MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default=" > + __MODULE_STRING(DEFAULT_TIMEOUT) ")"); > + > +static int imx_sc_wdt_ping(struct watchdog_device *wdog) > +{ > + struct arm_smccc_res res; > + > + arm_smccc_smc(IMX_SIP_TIMER, IMX_SIP_TIMER_PING_WDOG, > + 0, 0, 0, 0, 0, 0, &res); > + > + return 0; > +} > + > +static int imx_sc_wdt_start(struct watchdog_device *wdog) > +{ > + struct arm_smccc_res res; > + > + arm_smccc_smc(IMX_SIP_TIMER, IMX_SIP_TIMER_START_WDOG, > + 0, 0, 0, 0, 0, 0, &res); > + if (res.a0) > + return -EACCES; > + > + arm_smccc_smc(IMX_SIP_TIMER, IMX_SIP_TIMER_SET_WDOG_ACT, > + SC_TIMER_WDOG_ACTION_PARTITION, > + 0, 0, 0, 0, 0, &res); > + return res.a0 ? -EACCES : 0; > +} > + > +static int imx_sc_wdt_stop(struct watchdog_device *wdog) > +{ > + struct arm_smccc_res res; > + > + arm_smccc_smc(IMX_SIP_TIMER, IMX_SIP_TIMER_STOP_WDOG, > + 0, 0, 0, 0, 0, 0, &res); > + > + return res.a0 ? -EACCES : 0; > +} > + > +static int imx_sc_wdt_set_timeout(struct watchdog_device *wdog, > + unsigned int timeout) > +{ > + struct arm_smccc_res res; > + > + wdog->timeout = timeout; > + arm_smccc_smc(IMX_SIP_TIMER, IMX_SIP_TIMER_SET_TIMEOUT_WDOG, > + timeout * 1000, 0, 0, 0, 0, 0, &res); > + > + return res.a0 ? -EACCES : 0; > +} > + > +static const struct watchdog_ops imx_sc_wdt_ops = { > + .owner = THIS_MODULE, > + .start = imx_sc_wdt_start, > + .stop = imx_sc_wdt_stop, > + .ping = imx_sc_wdt_ping, > + .set_timeout = imx_sc_wdt_set_timeout, > +}; > + > +static const struct watchdog_info imx_sc_wdt_info = { > + .identity = "i.MX SC watchdog timer", > + .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | > + WDIOF_MAGICCLOSE | WDIOF_PRETIMEOUT, > +}; > + > +static int imx_sc_wdt_probe(struct platform_device *pdev) > +{ > + struct watchdog_device *imx_sc_wdd; > + int ret; > + > + imx_sc_wdd = devm_kzalloc(&pdev->dev, sizeof(*imx_sc_wdd), GFP_KERNEL); > + if (!imx_sc_wdd) > + return -ENOMEM; > + > + platform_set_drvdata(pdev, imx_sc_wdd); > + > + imx_sc_wdd->info = &imx_sc_wdt_info; > + imx_sc_wdd->ops = &imx_sc_wdt_ops; > + imx_sc_wdd->min_timeout = 1; > + imx_sc_wdd->max_timeout = MAX_TIMEOUT; > + imx_sc_wdd->parent = &pdev->dev; > + imx_sc_wdd->timeout = DEFAULT_TIMEOUT; > + > + ret = watchdog_init_timeout(imx_sc_wdd, timeout, &pdev->dev); > + if (ret) > + dev_warn(&pdev->dev, "Failed to set timeout value, using default\n"); > + > + watchdog_stop_on_reboot(imx_sc_wdd); > + watchdog_stop_on_unregister(imx_sc_wdd); > + > + ret = devm_watchdog_register_device(&pdev->dev, imx_sc_wdd); > + if (ret) { > + dev_err(&pdev->dev, "Failed to register watchdog device\n"); > + return ret; > + } > + > + return 0; > +} > + > +static int __maybe_unused imx_sc_wdt_suspend(struct device *dev) > +{ > + struct watchdog_device *imx_sc_wdd = dev_get_drvdata(dev); > + > + if (watchdog_active(imx_sc_wdd)) > + imx_sc_wdt_stop(imx_sc_wdd); > + > + return 0; > +} > + > +static int __maybe_unused imx_sc_wdt_resume(struct device *dev) > +{ > + struct watchdog_device *imx_sc_wdd = dev_get_drvdata(dev); > + > + if (watchdog_active(imx_sc_wdd)) > + imx_sc_wdt_start(imx_sc_wdd); > + > + return 0; > +} > + > +static SIMPLE_DEV_PM_OPS(imx_sc_wdt_pm_ops, > + imx_sc_wdt_suspend, imx_sc_wdt_resume); > + > +static const struct of_device_id imx_sc_wdt_dt_ids[] = { > + { .compatible = "fsl,imx-sc-wdt", }, > + { /* sentinel */ } > +}; > +MODULE_DEVICE_TABLE(of, imx_sc_wdt_dt_ids); > + > +static struct platform_driver imx_sc_wdt_driver = { > + .probe = imx_sc_wdt_probe, > + .driver = { > + .name = "imx-sc-wdt", > + .of_match_table = imx_sc_wdt_dt_ids, > + .pm = &imx_sc_wdt_pm_ops, > + }, > +}; > +module_platform_driver(imx_sc_wdt_driver); > + > +MODULE_AUTHOR("Robin Gong "); > +MODULE_DESCRIPTION("NXP i.MX system controller watchdog driver"); > +MODULE_LICENSE("GPL v2");