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[209.132.180.67]) by mx.google.com with ESMTP id v34si3711078pgk.320.2019.03.21.02.12.31; Thu, 21 Mar 2019 02:12:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728157AbfCUJLn (ORCPT + 99 others); Thu, 21 Mar 2019 05:11:43 -0400 Received: from foss.arm.com ([217.140.101.70]:52980 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727948AbfCUJLn (ORCPT ); Thu, 21 Mar 2019 05:11:43 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 45B7F374; Thu, 21 Mar 2019 02:11:42 -0700 (PDT) Received: from why.wild-wind.fr.eu.org (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0C5223F71A; Thu, 21 Mar 2019 02:11:39 -0700 (PDT) Date: Thu, 21 Mar 2019 09:11:35 +0000 From: Marc Zyngier To: chenjianguo Cc: Thomas Gleixner , Jason Cooper , "linux-kernel@vger.kernel.org" , "Liyou (leeyou, RTOS)" , "Joey Yan(Bo)" , "Xiaowei (C)" , "zhanghan (Q)" , Yangyingliang , yaohongbo , Linuxarm Subject: Re: [PATCH] mbigen: don't clear eventid when free_irq Message-ID: <20190321091135.5574b496@why.wild-wind.fr.eu.org> In-Reply-To: References: Organization: ARM Ltd X-Mailer: Claws Mail 3.17.3 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, 16 Mar 2019 11:15:03 +0000 chenjianguo wrote: > From: Jianguo Chen > > mbigen_write_msg clears eventid bits of a mbigen register > when free a interrupt, because msi_domain_deactivate memset > struct msg to zero. Then multiple mbigen pins with zero eventid > will report the same interrupt number. > > The eventid clear call trace: > free_irq > __free_irq > irq_shutdown > irq_domain_deactivate_irq > __irq_domain_deactivate_irq > __irq_domain_deactivate_irq > msi_domain_deactivate > platform_msi_write_msg > mbigen_write_msg > > Signed-off-by: Jianguo Chen > --- > drivers/irqchip/irq-mbigen.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/irqchip/irq-mbigen.c b/drivers/irqchip/irq-mbigen.c > index 567b29c..fad7291 100644 > --- a/drivers/irqchip/irq-mbigen.c > +++ b/drivers/irqchip/irq-mbigen.c > @@ -161,6 +161,9 @@ static void mbigen_write_msg(struct msi_desc *desc, > struct msi_msg *msg) > void __iomem *base = d->chip_data; > u32 val; > > + if (!msg->address_lo && !msg->address_hi) > + return; > + > base += get_mbigen_vec_reg(d->hwirq); > val = readl_relaxed(base); > For whatever reason, I couldn't apply this patch (even when fishing a copy of this email from the archives). It seems to be corrupted is various ways, so I had to write the patch from scratch, which is not the most reliable way to work. Good thing this was something trivial, I wouldn't do it for something more complicated. In the future, please make sure to use 'git send-email' to send your patches, as it is known to work correctly. Thanks, M. -- Without deviation from the norm, progress is not possible.