Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
From:   Anup Patel <Anup.Patel@wdc.com>
To:     Palmer Dabbelt <palmer@sifive.com>,
        Albert Ou <aou@eecs.berkeley.edu>
CC:     Atish Patra <Atish.Patra@wdc.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Christoph Hellwig <hch@infradead.org>,
        Mike Rapoport <rppt@linux.ibm.com>,
        "linux-riscv@lists.infradead.org" <linux-riscv@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Anup Patel <Anup.Patel@wdc.com>
Subject: [PATCH v2 0/5] Boot RISC-V kernel from any 4KB aligned address
Thread-Topic: [PATCH v2 0/5] Boot RISC-V kernel from any 4KB aligned address
Thread-Index: AQHU38sdwDGIWUY7eUuUlcce4MfVqQ==
Date:   Thu, 21 Mar 2019 09:47:36 +0000
Message-ID: <20190321094710.16552-1-anup.patel@wdc.com>
Accept-Language: en-US
Content-Language: en-US
x-ms-exchange-messagesentrepresentingtype: 1
x-mailer: git-send-email 2.17.1
x-originating-ip: [106.51.18.226]
x-ms-publictraffictype: Email
x-ms-office365-filtering-correlation-id: d5ba726e-f766-4584-de1d-08d6ade23f86
x-ms-office365-filtering-ht: Tenant
x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(7168020)(4627221)(201703031133081)(201702281549075)(8990200)(5600127)(711020)(4605104)(4618075)(2017052603328)(7153060)(7193020);SRVR:MN2PR04MB5757;
x-ms-traffictypediagnostic: MN2PR04MB5757:
wdcipoutbound: EOP-TRUE
x-microsoft-antispam-prvs: <MN2PR04MB5757BEE1170D9FC37C7DDE8B8D420@MN2PR04MB5757.namprd04.prod.outlook.com>
x-forefront-prvs: 0983EAD6B2
x-forefront-antispam-report: SFV:NSPM;SFS:(10019020)(39860400002)(376002)(346002)(136003)(366004)(396003)(189003)(199004)(54906003)(1076003)(68736007)(110136005)(316002)(6436002)(81166006)(2906002)(78486014)(8936002)(5660300002)(25786009)(50226002)(6486002)(52116002)(102836004)(6506007)(36756003)(386003)(26005)(9456002)(186003)(97736004)(99286004)(476003)(486006)(2616005)(44832011)(81156014)(105586002)(14454004)(4326008)(72206003)(106356001)(256004)(86362001)(55236004)(6512007)(71190400001)(7736002)(71200400001)(66066001)(3846002)(478600001)(305945005)(6116002)(53936002)(2171002)(8676002);DIR:OUT;SFP:1102;SCL:1;SRVR:MN2PR04MB5757;H:MN2PR04MB6061.namprd04.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;MX:1;A:1;
x-ms-exchange-senderadcheck: 1
x-microsoft-antispam-message-info: wBgsYAFQ75kzIHyXZGAJ77CniMyZP/yOG31QWscClRt2T++H4PQdVLu5GGxrSU6HetMUrI3x20CZ/wxurVLobWZU84ZDvGLsMPjvaEhbBEsA3trh+Fr6JfYXRZFV8u/8ySWHhkfbyaUnstiBlHwUGR36SOHSJVtpc+ttoJNL/oQ+gF+Ce6RdbmYfQdaBzt3vPUuxBkUyRE/Z6HshaD1WVQuxraHLg5tYC48TAHh8rekaIlar7O0k8LM186F0mUpOKfGGrdy9NRWwAZWftAVd/2b96LlwUVp4jX482eikfhqr2fA3LOngAvvP/VdhPnpp+VGmCN1CRt1SNtBnhdVNR0YewyH1fyMRHeAJ/l88YcYhQii8CZzRqhLwBQF6JL2SahKy3rhzQooAp7QYodvdMJ1KVEPFNvWnWi0h2iPzt1A=
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
MIME-Version: 1.0
X-OriginatorOrg: wdc.com
X-MS-Exchange-CrossTenant-Network-Message-Id: d5ba726e-f766-4584-de1d-08d6ade23f86
X-MS-Exchange-CrossTenant-originalarrivaltime: 21 Mar 2019 09:47:36.2683
 (UTC)
X-MS-Exchange-CrossTenant-fromentityheader: Hosted
X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86
X-MS-Exchange-CrossTenant-mailboxtype: HOSTED
X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB5757
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

This patchset primarily extends initial page table setup using fixmap
to boot Linux RISC-V kernel (64bit and 32bit) from any 4KB aligned address.

We also add 32bit defconfig to allow people to try 32bit Linux RISC-V
kernel as well.

The patchset is based on Linux-5.1-rc1 and tested on SiFive Unleashed
board and QEMU virt machine.

It can also be found in riscv_setup_vm_v2 branch of
https//github.com/avpatel/linux.git

Changes since v1:
- Add kconfig option BOOT_PAGE_ALIGNED to enable 4KB aligned booting
- Improved initial page table setup code to select best/biggest
  possible mapping size based on load address alignment
- Added PATCH4 to remove redundant trampoline page table
- Added PATCH5 to fix memory reservation in setup_bootmem()

Anup Patel (5):
  RISC-V: Add separate defconfig for 32bit systems
  RISC-V: Make setup_vm() independent of GCC code model
  RISC-V: Allow booting kernel from any 4KB aligned address
  RISC-V: Remove redundant trampoline page table
  RISC-V: Fix memory reservation in setup_bootmem()

 arch/riscv/Kconfig                  |  11 +
 arch/riscv/configs/rv32_defconfig   |  84 ++++++
 arch/riscv/include/asm/fixmap.h     |   5 +
 arch/riscv/include/asm/pgtable-64.h |   5 +
 arch/riscv/include/asm/pgtable.h    |   6 +-
 arch/riscv/kernel/head.S            |  15 +-
 arch/riscv/kernel/setup.c           |   4 +-
 arch/riscv/mm/init.c                | 391 +++++++++++++++++++++++-----
 8 files changed, 450 insertions(+), 71 deletions(-)
 create mode 100644 arch/riscv/configs/rv32_defconfig

--=20
2.17.1