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[209.132.180.67]) by mx.google.com with ESMTP id r17si4391744pgv.328.2019.03.21.10.54.25; Thu, 21 Mar 2019 10:54:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728744AbfCURwC (ORCPT + 99 others); Thu, 21 Mar 2019 13:52:02 -0400 Received: from Galois.linutronix.de ([146.0.238.70]:39022 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727823AbfCURwB (ORCPT ); Thu, 21 Mar 2019 13:52:01 -0400 Received: from p5492e2fc.dip0.t-ipconnect.de ([84.146.226.252] helo=nanos) by Galois.linutronix.de with esmtpsa (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1h71r8-0002dL-Nt; Thu, 21 Mar 2019 18:51:54 +0100 Date: Thu, 21 Mar 2019 18:51:54 +0100 (CET) From: Thomas Gleixner To: Stephane Eranian cc: Peter Zijlstra , Ingo Molnar , Jiri Olsa , LKML , tonyj@suse.com, nelson.dsouza@intel.com Subject: Re: [PATCH 1/8] perf/x86/intel: Fix memory corruption In-Reply-To: Message-ID: References: <20190314130113.919278615@infradead.org> <20190314130705.441549378@infradead.org> <20190319110549.GC5996@hirez.programming.kicks-ass.net> <20190319182041.GO5996@hirez.programming.kicks-ass.net> <20190320222220.GA2490@worktop.programming.kicks-ass.net> <20190321123849.GN6521@hirez.programming.kicks-ass.net> User-Agent: Alpine 2.21 (DEB 202 2017-01-01) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 21 Mar 2019, Stephane Eranian wrote: > On Thu, Mar 21, 2019 at 9:45 AM Thomas Gleixner wrote: > > > > On Thu, 21 Mar 2019, Peter Zijlstra wrote: > > > Subject: perf/x86/intel: Initialize TFA MSR > > > > > > Stephane reported that we don't initialize the TFA MSR, which could lead > > > to trouble if the RESET value is not 0 or on kexec. > > > > That sentence doesn't parse. > > > > Stephane reported that the TFA MSR is not initialized by the kernel, but > > the TFA bit could set by firmware or as a leftover from a kexec, which > > makes the state inconsistent. > > > Correct. This is what I meant. > The issue is what does the kernel guarantee when it boots? > > I see: > static bool allow_tsx_force_abort = true; > > Therefore you must ensure the MSR is set to reflect that state on boot. > So you have to force it to that value to be in sync which is what your > new patch is doing. The initial state should be that the MSR TFA bit is 0. The software state is a different beast. allow_tsx_force_abort false Do not set MSR TFA bit (Make TSX work with PMC3) and exclude PMC3 from being used. true Set the MSR TFA bit when PMC3 is used by perf, clear it when PMC3 is not longer in use. Now, if the firmware or the kexec has the TFA bit set in the MSR and PMC3 is not in use then TSX always aborts pointlessly. It's not a fatal isseu, but it's inconsistent. So independent of the state of allow_tsx_force_abort the kernel has to clear the MSR TSA bit when the CPUs are brought up. The state of allow_tsx_force_abort is solely relevant after CPUs coming up to decide whether PMC3 can be used by perf or not. Thanks, tglx