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[209.132.180.67]) by mx.google.com with ESMTP id s4si6457294pgp.364.2019.03.22.05.45.59; Fri, 22 Mar 2019 05:46:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388420AbfCVMp1 (ORCPT + 99 others); Fri, 22 Mar 2019 08:45:27 -0400 Received: from bhuna.collabora.co.uk ([46.235.227.227]:54824 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730518AbfCVMpT (ORCPT ); Fri, 22 Mar 2019 08:45:19 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: gportay) with ESMTPSA id 57870260891 Date: Fri, 22 Mar 2019 08:45:26 -0400 From: =?utf-8?B?R2HDq2w=?= PORTAY To: Matthias Kaehlcke Cc: Mark Rutland , devicetree@vger.kernel.org, Derek Basehore , Heiko Stuebner , linux-pm@vger.kernel.org, Brian Norris , Douglas Anderson , linux-kernel@vger.kernel.org, Chanwoo Choi , Kyungmin Park , Rob Herring , Klaus Goger , MyungJoo Ham , Enric Balletbo i Serra , linux-rockchip@lists.infradead.org, Randy Li , kernel@collabora.com, linux-arm-kernel@lists.infradead.org, Lin Huang Subject: Re: [PATCH v2 3/5] devfreq: rk3399_dmc: Pass ODT and auto power down parameters to TF-A. Message-ID: <20190322124525.ge5thq4a7c6ufcra@archlinux.localdomain> References: <20190319181323.22804-1-gael.portay@collabora.com> <20190319181323.22804-4-gael.portay@collabora.com> <20190320003352.GN112750@google.com> <20190320215013.43zgvyn5frnb3yud@archlinux.localdomain> <20190320220223.GP112750@google.com> <20190321231055.j7z23f3k3rcngq4u@archlinux.localdomain> <20190322000107.GU112750@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190322000107.GU112750@google.com> User-Agent: NeoMutt/20180716 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Matthias, On Thu, Mar 21, 2019 at 05:01:07PM -0700, Matthias Kaehlcke wrote: > > ... > > > > So, for a reason that I ignore, if we try to save unecessary calls to > > ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD (odt_enable has not changed since > > last call), we get stalled in the call to ROCKCHIP_SIP_CONFIG_SET_RAGE > > that follows. The function arm_smccc_smc never returns and the device > > hard hang. > > Thanks for giving it a try! > > Did your code ensure to perform the SMC call for the first frequency > change? If not the problem could be that the DDR PD timings and ODT > resistors are not properly configured for the new frequency. > The DRAM_ODT_PD SMC call is supposed to be performed before the DRAM_SET_RATE; unless someone else is doing the set_rate. Does the ODT resistors should be configured for every existing frequency? > In case you already did this or it doesn't help I think it's fine to > just do the call always, we can always revisit this later. > Okay, sounds good. > > Thanks to your remark, I have also fixed an issue with the odt_dis_freq > > value. Its value is initialized to 0 in the probe function. Thus the > > odt_enable is always true (target_rate > 0). I moved its initialization > > after the timings are parsed from the device-tree; its value is now none > > zero (333000000 in my case). > > Great! Gael