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From:   Anup Patel <anup@brainfault.org>
Date:   Sat, 23 Mar 2019 16:45:12 +0530
Message-ID: <CAAhSdy2MNA3A-vYD+WJqZAF9L8nScVjh7ZNQDdPpJNB+=BoWkw@mail.gmail.com>
Subject: Re: [PATCH] clocksource/drivers/riscv: Fix clocksource mask
To:     Atish Patra <atish.patra@wdc.com>
Cc:     "linux-kernel@vger.kernel.org List" <linux-kernel@vger.kernel.org>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Daniel Lezcano <daniel.lezcano@linaro.org>,
        linux-riscv@lists.infradead.org,
        Palmer Dabbelt <palmer@sifive.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Anup Patel <Anup.Patel@wdc.com>,
        Damien Le Moal <Damien.LeMoal@wdc.com>
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Sender: linux-kernel-owner@vger.kernel.org
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On Sat, Mar 23, 2019 at 3:24 AM Atish Patra <atish.patra@wdc.com> wrote:
>
> For all riscv architectures (RV32, RV64 and RV128), the clocksource
> is a 64 bit incrementing counter.
>
> Fix the clock source mask accordingly.
>
> Tested on both 64bit and 32 bit virt machine in QEMU.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
>  drivers/clocksource/timer-riscv.c | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
> index e8163693..5e6038fb 100644
> --- a/drivers/clocksource/timer-riscv.c
> +++ b/drivers/clocksource/timer-riscv.c
> @@ -58,7 +58,7 @@ static u64 riscv_sched_clock(void)
>  static DEFINE_PER_CPU(struct clocksource, riscv_clocksource) = {
>         .name           = "riscv_clocksource",
>         .rating         = 300,
> -       .mask           = CLOCKSOURCE_MASK(BITS_PER_LONG),
> +       .mask           = CLOCKSOURCE_MASK(64),
>         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
>         .read           = riscv_clocksource_rdtime,
>  };
> @@ -120,8 +120,7 @@ static int __init riscv_timer_init_dt(struct device_node *n)
>                 return error;
>         }
>
> -       sched_clock_register(riscv_sched_clock,
> -                       BITS_PER_LONG, riscv_timebase);
> +       sched_clock_register(riscv_sched_clock, 64, riscv_timebase);
>
>         error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING,
>                          "clockevents/riscv/timer:starting",
> --
> 2.21.0
>

Looks good to me.

It would be great if you can add "Fixes:" line and
"Cc: stable@vger.kernel.org"

Reviewed-by: Anup Patel <anup@brainfault.org>

Regards,
Anup