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[209.132.180.67]) by mx.google.com with ESMTP id d4si13531547pgk.501.2019.03.25.05.43.56; Mon, 25 Mar 2019 05:44:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731156AbfCYMlv (ORCPT + 99 others); Mon, 25 Mar 2019 08:41:51 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:55811 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1731096AbfCYMlv (ORCPT ); Mon, 25 Mar 2019 08:41:51 -0400 X-UUID: a4fd0f08366f4a51b2a7bd1bdc8f5e0f-20190325 X-UUID: a4fd0f08366f4a51b2a7bd1bdc8f5e0f-20190325 Received: from mtkcas09.mediatek.inc [(172.21.101.178)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1507453066; Mon, 25 Mar 2019 20:41:45 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 25 Mar 2019 20:41:43 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 25 Mar 2019 20:41:42 +0800 From: Zhiyong Tao To: , , , , CC: , , , , , , , , , , , , , Subject: [PATCH RESEND v3 3/4] arm64: dts: mt8183: add pintcrl device node Date: Mon, 25 Mar 2019 20:41:36 +0800 Message-ID: <20190325124137.6117-4-zhiyong.tao@mediatek.com> X-Mailer: git-send-email 2.12.5 In-Reply-To: <20190325124137.6117-1-zhiyong.tao@mediatek.com> References: <20190325124137.6117-1-zhiyong.tao@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The commit adds pintcrl device node for mt8183 Signed-off-by: Zhiyong Tao --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 75c4881bbe5e..cf92504e2a9b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -9,7 +9,7 @@ #include #include #include - +#include "mt8183-pinfunc.h" / { compatible = "mediatek,mt8183"; interrupt-parent = <&sysirq>; @@ -197,6 +197,30 @@ #clock-cells = <1>; }; + pio: pinctrl@10005000 { + compatible = "mediatek,mt8183-pinctrl"; + reg = <0 0x10005000 0 0x1000>, + <0 0x11f20000 0 0x1000>, + <0 0x11e80000 0 0x1000>, + <0 0x11e70000 0 0x1000>, + <0 0x11e90000 0 0x1000>, + <0 0x11d30000 0 0x1000>, + <0 0x11d20000 0 0x1000>, + <0 0x11c50000 0 0x1000>, + <0 0x11f30000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "iocfg0", "iocfg1", "iocfg2", + "iocfg3", "iocfg4", "iocfg5", + "iocfg6", "iocfg7", "iocfg8", + "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 192>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <2>; + }; + scpsys: syscon@10006000 { compatible = "mediatek,mt8183-scpsys", "syscon"; #power-domain-cells = <1>; -- 2.12.5