Received: by 2002:ac0:bc90:0:0:0:0:0 with SMTP id a16csp3251323img; Mon, 25 Mar 2019 06:47:15 -0700 (PDT) X-Google-Smtp-Source: APXvYqyaAu1w/WsNmM1ZnP9gy9F9p7hecXXXv6Y/HG+gfT+zF9mTks0culRc+nqzmA4o7J/l3SB0 X-Received: by 2002:a62:fb0a:: with SMTP id x10mr19384236pfm.179.1553521635358; Mon, 25 Mar 2019 06:47:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553521635; cv=none; d=google.com; s=arc-20160816; b=OVQignJtUwKVH/PsYgR8HIh5V6uQd5zUiHNH0NiJWFgz6+Y1h+ux75uBgd9LlcOKid b4XXPEPxx/kJtjNnMt7r5lMyA8WPo5o5Lwo7tGWCVbscYeftyqWQzIN3rMleskldq22n 85lhtbwETa3jv5bo9MPEG/4mArpUe26g7UVIsmeiyMfMONj+bTTk6Z1C1sz7RJKIDjEx Fbarp0gczPDcGgA5l0pwuRf8tQbLnuJB/cjOVl6ovbX+6l/UxrTiLi40XmvzS24DfQLo CiMGvjMjemfd9+5UDEzRJW8P/UCd7QllsbHEWAQyieyTvl/7io+CLOrYRmryWoLsvv3u f2cA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:user-agent:in-reply-to :content-transfer-encoding:content-disposition:mime-version :references:message-id:subject:cc:to:from:date; bh=NoZQ4Ps6ubhiIwqN8A+Ru6bxvUIWjuEb3v+pP0/Kmq8=; b=UqRpbDBhArY46e69Vrcf2wJWKwV2QkyRW3ScgCUnak6hjR7NdGTTkwpwI/Ql4UNt+m KukbtUzgbzBp6xjtqCZRkmUbjrgG2qHiUkSOWb8rWZCvD1NyLKC2Y4GxlIv7WQcDS88j We2TBot6p8al1T0ZIGvFAfMABstG+bdnUs+RHvfN4EGIg4TGYsWoRCuuupUkaS5S3BnX SyrcsQpUAqlYlg985hCi32W6B6YKIm66PFO/gU0A8Ggqyqjgvz3h0ZJRbO2hsJdlMXmU nhcWYqRhfk+myN3vNNMFNMGb3qDHB9gkIBgSANU9m8IWzje/Xh8U7WXxlqVvM2e9tdIO grYg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=8bytes.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y6si1029066plp.201.2019.03.25.06.47.00; Mon, 25 Mar 2019 06:47:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=8bytes.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729077AbfCYNqE (ORCPT + 99 others); Mon, 25 Mar 2019 09:46:04 -0400 Received: from 8bytes.org ([81.169.241.247]:59000 "EHLO theia.8bytes.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725554AbfCYNqE (ORCPT ); Mon, 25 Mar 2019 09:46:04 -0400 Received: by theia.8bytes.org (Postfix, from userid 1000) id D2B422D8; Mon, 25 Mar 2019 14:46:02 +0100 (CET) Date: Mon, 25 Mar 2019 14:46:01 +0100 From: "joro@8bytes.org" To: "Suthikulpanit, Suravee" Cc: "linux-kernel@vger.kernel.org" , "kvm@vger.kernel.org" , "iommu@lists.linux-foundation.org" , "pbonzini@redhat.com" , "rkrcmar@redhat.com" Subject: Re: [PATCH] svm/avic: iommu/amd: Flush IOMMU IRT after update all entries Message-ID: <20190325134601.GB25350@8bytes.org> References: <20190320081432.2606-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20190320081432.2606-1-suravee.suthikulpanit@amd.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Mar 20, 2019 at 08:14:56AM +0000, Suthikulpanit, Suravee wrote: > When AVIC is enabled and the VM has discrete device assignment, > the interrupt remapping table (IRT) is used to keep track of which > destination APIC ID the IOMMU will inject the device interrput to. > > This means every time a vcpu is blocked or context-switched (i.e. > vcpu_blocking/unblocking() and vcpu_load/put()), the information > in IRT must be updated and the IOMMU IRT flush command must be > issued. > > The current implementation flushes IOMMU IRT every time an entry > is modified. If the assigned device has large number of interrupts > (hence large number of entries), this would add large amount of > overhead to vcpu context-switch. Instead, this can be optmized by > only flush IRT once per vcpu context-switch per device after all > IRT entries are modified. > > The function amd_iommu_update_ga() is refactored to only update > IRT entry, while the amd_iommu_sync_ga() is introduced to allow > IRT flushing to be done separately. > > Cc: Joerg Roedel > Cc: Radim Krčmář > Cc: Paolo Bonzini > Signed-off-by: Suravee Suthikulpanit > --- > arch/x86/kvm/svm.c | 35 ++++++++++++++++++++++++++++++++++- > drivers/iommu/amd_iommu.c | 20 +++++++++++++++++--- > include/linux/amd-iommu.h | 13 ++++++++++--- > 3 files changed, 61 insertions(+), 7 deletions(-) For the IOMMU parts: Acked-by: Joerg Roedel