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received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: kf2UGiHPN0qk1WXsv9y1kFLMScXNhwQXS5aLRWr1k4gWEdoMRzTdzK1lOI9dmeEimGwRrfKURotj+0nb3er4BZnt9mpdCIFnJGiZ5HywPp0IPHIU0KWbevUjL9gqnoR/lhqbOBb8tE2hDTcGD4pnTLytEAVNhp5/IIgqdY5sMIp48K27QJXOuSRi1RJzgPVgsZ7N/V0MAXNL0gH5XrRiELMbAmknQu/tP1fzDjg8rw2ZGgPpog/9/GtdYOPVLlrV0ZLM6y+14EQHyjNirjCNcR1LrLQ+aipK7a2gjKqsZFHhsSz8hpE3/XjNuL2zJtU6FdfcLkVSNS+cVKV6duHWrqihVc/GdbtZfsVX96YB/b2E6BIawSDmrjT/1C4G6ly1bDhLyNTNHZKJJjT6MsjgEDNrhtsFOdjYuh5xiEgZAOE= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4c1ba7d7-84ca-495b-4de6-08d6b136319f X-MS-Exchange-CrossTenant-originalarrivaltime: 25 Mar 2019 15:26:03.7167 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB6000 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org >-----Original Message----- >From: Vladimir Oltean >Sent: Monday, March 25, 2019 11:31 AM >To: shawnguo@kernel.org; Leo Li ; Claudiu Manoil > >Cc: robh+dt@kernel.org; linux-arm-kernel@lists.infradead.org; >devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; >netdev@vger.kernel.org; davem@davemloft.net; Vladimir Oltean > >Subject: [PATCH] ARM: dts: ls1021: Fix SGMII PCS link remaining down after= PHY >disconnect > >Each eTSEC MAC has its own TBI (SGMII) PCS and private MDIO bus. >But due to a DTS oversight, both SGMII-compatible MACs of the LS1021 SoC a= re >pointing towards the same internal PCS. Therefore nobody is controlling th= e >internal PCS of eTSEC0. > >Upon initial ndo_open, the SGMII link is ok by virtue of U-boot initializa= tion. But >upon an ifdown/ifup sequence, the code path from ndo_open -> init_phy -> >gfar_configure_serdes does not get executed for the PCS of eTSEC0 (and is >executed twice for MAC eTSEC1). So the SGMII link remains down for eTSEC0. >On the LS1021A-TWR board, to signal this failure condition, the PHY driver= keeps >printing >'803x_aneg_done: SGMII link is not ok'. > >Fixes: 055223d4d22d ("ARM: dts: ls1021a: Enable the eTSEC ports on QDS and >TWR") >Signed-off-by: Vladimir Oltean Reviewed-by: Claudiu Manoil