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From:   "Ghannam, Yazen" <Yazen.Ghannam@amd.com>
To:     "linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>
CC:     "Ghannam, Yazen" <Yazen.Ghannam@amd.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "bp@alien8.de" <bp@alien8.de>
Subject: [PATCH] EDAC/amd64: Use maximum channel count for the EDAC channel
 layer size
Thread-Topic: [PATCH] EDAC/amd64: Use maximum channel count for the EDAC
 channel layer size
Thread-Index: AQHU40oCFvOyy4xqaEiYK0CJr0cY8Q==
Date:   Mon, 25 Mar 2019 20:33:30 +0000
Message-ID: <20190325203319.7603-1-Yazen.Ghannam@amd.com>
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From: Yazen Ghannam <yazen.ghannam@amd.com>

The AMD64 EDAC module current hardcodes the EDAC channel layer size
(count) to two. Future AMD systems may have more channels than this.

Set the EDAC channel layer size equal to the maximum number of channels
possible for the system. On Family 17h and later, this is set in the
num_umcs variable. Older systems will continue to use two as the
default.

Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
 drivers/edac/amd64_edac.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index b7617fad282c..4c0239aeff2f 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -3357,8 +3357,14 @@ static int init_one_instance(unsigned int nid)
 	 * Always allocate two channels since we can have setups with DIMMs on
 	 * only one channel. Also, this simplifies handling later for the price
 	 * of a couple of KBs tops.
+	 *
+	 * On Fam17h+, the number of controllers may be greater than two. So set
+	 * the size equal to the maximum number of UMCs.
 	 */
-	layers[1].size =3D 2;
+	if (pvt->fam >=3D 0x17)
+		layers[1].size =3D num_umcs;
+	else
+		layers[1].size =3D 2;
 	layers[1].is_virt_csrow =3D false;
=20
 	mci =3D edac_mc_alloc(nid, ARRAY_SIZE(layers), layers, 0);
--=20
2.17.1