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[209.132.180.67]) by mx.google.com with ESMTP id o14si15648433pgv.310.2019.03.26.05.29.09; Tue, 26 Mar 2019 05:29:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729662AbfCZM2f (ORCPT + 99 others); Tue, 26 Mar 2019 08:28:35 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:34111 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726140AbfCZM2f (ORCPT ); Tue, 26 Mar 2019 08:28:35 -0400 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x2QCMJbC010377; Tue, 26 Mar 2019 13:28:15 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2rf4ybveea-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 26 Mar 2019 13:28:15 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id A2F1531; Tue, 26 Mar 2019 12:28:14 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag3node2.st.com [10.75.127.8]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 58DC95773; Tue, 26 Mar 2019 12:28:14 +0000 (GMT) Received: from [10.48.0.204] (10.75.127.48) by SFHDAG3NODE2.st.com (10.75.127.8) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 26 Mar 2019 13:28:13 +0100 Subject: Re: [PATCH v2 0/6] Add nvmem support on STM32 To: Fabrice Gasnier , , CC: , , , , , , References: <1551349196-8956-1-git-send-email-fabrice.gasnier@st.com> From: Alexandre Torgue Message-ID: <694a9e17-c864-bc11-6fdc-8f9f67e30e7c@st.com> Date: Tue, 26 Mar 2019 13:27:58 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.5.1 MIME-Version: 1.0 In-Reply-To: <1551349196-8956-1-git-send-email-fabrice.gasnier@st.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.75.127.48] X-ClientProxiedBy: SFHDAG1NODE2.st.com (10.75.127.2) To SFHDAG3NODE2.st.com (10.75.127.8) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-03-26_09:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Fabrice On 2/28/19 11:19 AM, Fabrice Gasnier wrote: > Non volatile memory area is available on STM32. It contains various > factory programmed information such as unique device ID, analog calibration... > This patchset adds: > - NVMEM support to access stm32 data cells > - helper to read 16 bits cells. > > --- > Changes in v2: > - update "st,stm32f4-otp" compatible as discussed with Rob > - add stm32f429 dts > - add core helper to read 16 bits cells > > Fabrice Gasnier (6): ... > ARM: dts: stm32: Add romem and temperature calibration on stm32mp157c > ARM: dts: stm32: Add romem and temperature calibration on stm32f429 DT patches applied on stm32-next. Regards Alex