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From:   Rob Herring <robh@kernel.org>
Date:   Tue, 26 Mar 2019 08:20:16 -0500
Message-ID: <CAL_JsqJrct6atOOto4hdDaRZKhnPda7ATV=7+OofWNUJFD=i8Q@mail.gmail.com>
Subject: Re: [PATCH v7 2/3] dt-bindings: phy: Add documentation for mixel dphy
To:     =?UTF-8?Q?Guido_G=C3=BCnther?= <agx@sigxcpu.org>
Cc:     Maxime Ripard <maxime.ripard@bootlin.com>,
        dri-devel <dri-devel@lists.freedesktop.org>,
        "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" 
        <linux-arm-kernel@lists.infradead.org>,
        Robert Chiras <robert.chiras@nxp.com>,
        Sam Ravnborg <sam@ravnborg.org>,
        Fabio Estevam <festevam@gmail.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
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On Mon, Mar 25, 2019 at 9:14 AM Guido G=C3=BCnther <agx@sigxcpu.org> wrote:
>
> Add support for the MIXEL DPHY IP as found in the NXP's i.MX8MQ.

Please use get_maintainers.pl and send patches to the correct lists.

>
> Signed-off-by: Guido G=C3=BCnther <agx@sigxcpu.org>
> Reviewed-by: Sam Ravnborg <sam@ravnborg.org>
> ---
>  .../bindings/phy/mixel,mipi-dsi-phy.txt       | 29 +++++++++++++++++++
>  1 file changed, 29 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/mixel,mipi-dsi-=
phy.txt
>
> diff --git a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt=
 b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt
> new file mode 100644
> index 000000000000..d3646580412a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt
> @@ -0,0 +1,29 @@
> +Mixel DSI PHY for i.MX8
> +
> +The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along =
the
> +MIPI-DSI IP from Northwest Logic). It represents the physical layer for =
the
> +electrical signals for DSI.
> +
> +Required properties:
> +- compatible: Must be:
> +  - "mixel,imx8mq-mipi-dphy"
> +- clocks: Must contain an entry for each entry in clock-names.
> +- clock-names: Must contain the following entries:
> +  - "phy_ref": phandle and specifier referring to the DPHY ref clock
> +- reg: the register range of the PHY controller
> +- #phy-cells: number of cells in PHY, as defined in
> +  Documentation/devicetree/bindings/phy/phy-bindings.txt
> +  this must be <0>
> +
> +Optional properties:
> +- power-domains: phandle to power domain
> +
> +Example:
> +       mipi_dphy: mipi_dphy@30A0030 {

dphy@30a0030

> +               compatible =3D "mixel,imx8mq-mipi-dphy";
> +               clocks =3D <&clk IMX8MQ_CLK_DSI_PHY_REF>;
> +               clock-names =3D "phy_ref";
> +               reg =3D <0x30A00300 0x100>;
> +               power-domains =3D <&pd_mipi0>;
> +               #phy-cells =3D <0>;
> +        };
> --
> 2.20.1
>
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