Received: by 2002:ac0:bc90:0:0:0:0:0 with SMTP id a16csp4378014img;
        Tue, 26 Mar 2019 08:16:57 -0700 (PDT)
X-Google-Smtp-Source: APXvYqzFjrRpMb0s0NrtnX+qifw5wMSux3813Kw99fwCSRgoeDPF+qRvjUxKYvT4VMEfn3MWiI39
X-Received: by 2002:a65:4844:: with SMTP id i4mr28618724pgs.347.1553613417885;
        Tue, 26 Mar 2019 08:16:57 -0700 (PDT)
ARC-Seal: i=1; a=rsa-sha256; t=1553613417; cv=none;
        d=google.com; s=arc-20160816;
        b=bJ0wstJUWsazv6wDWj1lFsEWANd2HrUVEHlFWV6ZncRGT87MaCb75oPQA4Yp4YJtW4
         0ziudISIdpnY2ST6so84EJ+4wrxglmQd+4qSegz8TjXXpdwesFhJZTv4rDYFu2dK6HLs
         FTkwvc3Sx/Ihe8U71zWyWoWFPlqurkOB+yj652QtNKqTmnT3M80/vwlHZumOfPDn0ZyT
         p9OjuaQcPKF2k4pNuNMX09JNpD+RY4/0sKjYe680geaCLNkvUKwoO+Z9EiP1GWvFKFTx
         pxmalxvPn2gtlX2l6VjZzKd3H1DjJf8f74l5WCgAhx1me/TwdJzmetvauzJBqhYVaL0H
         todw==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816;
        h=list-id:precedence:sender:dkim-signature:mime-version:references
         :in-reply-to:message-id:date:subject:cc:to:from;
        bh=hPLUL9Di6m8xA5FM/T73AfF2DuF3x/3OnB8VBnM4nyU=;
        b=Pd+1moxvXT0y1cBkihGE7Mion6/aR0NxOI4LFyibt5i2YAIt3zWWeMwGBWNMplrfnD
         TUYGw+2k87k4Kx+WuAx4MvzQJqdj5gCF6ieAFp0NL9hSNg8+w7i/EBD3ib3lXnuWd0Nv
         AsEawbn3XsXuPc27hTPFfny1539WdPbfJz0Zi/u6BhKnsnU685ipo6MdwAL7CE0E4wYk
         ZBow7SVGiCatUliXpEEA7iC11btqu8cWiX+lYxKR6KLXJe2Avzn9nDvR9q7MTMkq78Ql
         3ls2ZDDaq9rV2LJKmIZUoFTlVFPiRqgyChfPTegPv7YDCs2ou6ULOrbfB2dWmmf66l9+
         Uf0A==
ARC-Authentication-Results: i=1; mx.google.com;
       dkim=pass header.i=@nvidia.com header.s=n1 header.b="EefYt/rQ";
       spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org;
       dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com
Return-Path: <linux-kernel-owner@vger.kernel.org>
Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67])
        by mx.google.com with ESMTP id t23si16355128pfa.64.2019.03.26.08.16.42;
        Tue, 26 Mar 2019 08:16:57 -0700 (PDT)
Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
Authentication-Results: mx.google.com;
       dkim=pass header.i=@nvidia.com header.s=n1 header.b="EefYt/rQ";
       spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org;
       dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
        id S1732022AbfCZPOd (ORCPT <rfc822;plaguedbypenguins@gmail.com>
        + 99 others); Tue, 26 Mar 2019 11:14:33 -0400
Received: from hqemgate16.nvidia.com ([216.228.121.65]:18251 "EHLO
        hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org
        with ESMTP id S1731715AbfCZPOd (ORCPT
        <rfc822;linux-kernel@vger.kernel.org>);
        Tue, 26 Mar 2019 11:14:33 -0400
Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA)
        id <B5c9a41d60000>; Tue, 26 Mar 2019 08:14:30 -0700
Received: from hqmail.nvidia.com ([172.20.161.6])
  by hqpgpgate101.nvidia.com (PGP Universal service);
  Tue, 26 Mar 2019 08:14:31 -0700
X-PGP-Universal: processed;
        by hqpgpgate101.nvidia.com on Tue, 26 Mar 2019 08:14:31 -0700
Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL105.nvidia.com
 (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 26 Mar
 2019 15:14:31 +0000
Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com
 (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend
 Transport; Tue, 26 Mar 2019 15:14:31 +0000
Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121)
        id <B5c9a41ce0000>; Tue, 26 Mar 2019 08:14:31 -0700
From:   Vidya Sagar <vidyas@nvidia.com>
To:     <bhelgaas@google.com>, <robh+dt@kernel.org>,
        <mark.rutland@arm.com>, <thierry.reding@gmail.com>,
        <jonathanh@nvidia.com>, <kishon@ti.com>, <catalin.marinas@arm.com>,
        <will.deacon@arm.com>, <lorenzo.pieralisi@arm.com>,
        <jingoohan1@gmail.com>, <gustavo.pimentel@synopsys.com>,
        <mperttunen@nvidia.com>, <vidyas@nvidia.com>, <tiwai@suse.de>,
        <spujar@nvidia.com>, <skomatineni@nvidia.com>,
        <liviu.dudau@arm.com>, <krzk@kernel.org>, <heiko@sntech.de>,
        <horms+renesas@verge.net.au>, <olof@lixom.net>,
        <maxime.ripard@bootlin.com>, <andy.gross@linaro.org>,
        <bjorn.andersson@linaro.org>, <jagan@amarulasolutions.com>,
        <enric.balletbo@collabora.com>, <ezequiel@collabora.com>,
        <stefan.wahren@i2se.com>, <marc.w.gonzalez@free.fr>,
        <l.stach@pengutronix.de>, <tpiepho@impinj.com>,
        <hayashi.kunihiko@socionext.com>, <yue.wang@amlogic.com>,
        <shawn.lin@rock-chips.com>, <xiaowei.bao@nxp.com>
CC:     <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
        <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>, <kthota@nvidia.com>,
        <mmaddireddy@nvidia.com>
Subject: [PATCH 02/10] PCI: perform dbi regs write lock towards the end
Date:   Tue, 26 Mar 2019 20:43:19 +0530
Message-ID: <1553613207-3988-3-git-send-email-vidyas@nvidia.com>
X-Mailer: git-send-email 2.7.4
In-Reply-To: <1553613207-3988-1-git-send-email-vidyas@nvidia.com>
References: <1553613207-3988-1-git-send-email-vidyas@nvidia.com>
X-NVConfidentiality: public
MIME-Version: 1.0
Content-Type: text/plain
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1;
        t=1553613270; bh=hPLUL9Di6m8xA5FM/T73AfF2DuF3x/3OnB8VBnM4nyU=;
        h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer:
         In-Reply-To:References:X-NVConfidentiality:MIME-Version:
         Content-Type;
        b=EefYt/rQbDdaP2v2HJBMqtFP6hEyjkHDmLObi39nDEABMZuH4giSQaRJzFODvADmT
         9WVnJTRmS5/3NbiKj7Tuv17KT5R5ceiBfv3KOKr+fhClodeAX4lzcIjUgfMxkiNNfw
         J1EoSLHf3YqJrkjNnqpkq4Kqj+vka/9x8Zf8gLtVW3AdCFtiSb8aF4DbREyOyhvq37
         2ssaufVV+mgTGMt0Co4pTasU46uwZ1iNga9Cigq5gv4ucm4E/OdPwOTodhO7tFFC6i
         Gyz79CG0QMoE2DVQrecL3NFJCsGKOvm6OvxTjy2QCqItUYSefckx2Aoi5iyvXN4Adm
         /rv0bK0WTKvgw==
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

Remove multiple write enable and disable sequences of dbi registers as
Tegra194 implements writes to BAR-0 register (offset: 0x10) controlled by
DBI write-lock enable bit thereby not allowing any further writes to BAR-0
register in config space to take place. Hence disabling write permission
only towards the end.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
 drivers/pci/controller/dwc/pcie-designware-host.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 15add3cf3945..e17213f2217e 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -670,7 +670,6 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
 	val &= 0xffff00ff;
 	val |= 0x00000100;
 	dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
-	dw_pcie_dbi_ro_wr_dis(pci);
 
 	/* Setup bus numbers */
 	val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
@@ -710,8 +709,6 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
 
 	dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
 
-	/* Enable write permission for the DBI read-only register */
-	dw_pcie_dbi_ro_wr_en(pci);
 	/* Program correct class for RC */
 	dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
 	/* Better disable write permission right after the update */
-- 
2.7.4