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From:   =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= <j.neuschaefer@gmx.net>
To:     linux-clk@vger.kernel.org
Cc:     Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Shawn Guo <shawnguo@kernel.org>,
        Sascha Hauer <s.hauer@pengutronix.de>,
        Pengutronix Kernel Team <kernel@pengutronix.de>,
        Fabio Estevam <festevam@gmail.com>,
        NXP Linux Team <linux-imx@nxp.com>,
        =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= <j.neuschaefer@gmx.net>,
        Lucas Stach <l.stach@pengutronix.de>,
        Michael Grzeschik <m.grzeschik@pengutronix.de>,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        Aisheng Dong <aisheng.dong@nxp.com>
Subject: [PATCH v2 2/2] clk: imx5: Fix i.MX50 ESDHC clock registers
Date:   Tue, 26 Mar 2019 19:22:58 +0100
Message-Id: <20190326182258.21945-3-j.neuschaefer@gmx.net>
In-Reply-To: <20190326182258.21945-1-j.neuschaefer@gmx.net>
References: <20190326182258.21945-1-j.neuschaefer@gmx.net>
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Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

The MUX bits for esdhc_{a,c,d}_sel are shifted by one bit within CSCMR1,
because esdhc_b_sel (ESDHC3_CLK_SEL in the Reference Manual) is extended
by one bit.

Signed-off-by: Jonathan Neusch=C3=A4fer <j.neuschaefer@gmx.net>
=2D--
v2:
- Split into two patches, as suggested by Aisheng Dong
- Extended the commit message slightly

v1:
https://lore.kernel.org/lkml/20190318231737.8459-1-j.neuschaefer@gmx.net/
=2D--
 drivers/clk/imx/clk-imx51-imx53.c | 40 +++++++++++++++++++++++--------
 1 file changed, 30 insertions(+), 10 deletions(-)

diff --git a/drivers/clk/imx/clk-imx51-imx53.c b/drivers/clk/imx/clk-imx51=
-imx53.c
index 3c188aa37cd7..c85ebd74a8a5 100644
=2D-- a/drivers/clk/imx/clk-imx51-imx53.c
+++ b/drivers/clk/imx/clk-imx51-imx53.c
@@ -187,16 +187,10 @@ static void __init mx5_clocks_common_init(void __iom=
em *ccm_base)
 	clk[IMX5_CLK_UART_PRED]		=3D imx_clk_divider("uart_pred", "uart_sel", MX=
C_CCM_CSCDR1, 3, 3);
 	clk[IMX5_CLK_UART_ROOT]		=3D imx_clk_divider("uart_root", "uart_pred", M=
XC_CCM_CSCDR1, 0, 3);

-	clk[IMX5_CLK_ESDHC_A_SEL]	=3D imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1,=
 20, 2,
-						standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
-	clk[IMX5_CLK_ESDHC_B_SEL]	=3D imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1,=
 16, 2,
-						standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
 	clk[IMX5_CLK_ESDHC_A_PRED]	=3D imx_clk_divider("esdhc_a_pred", "esdhc_a_=
sel", MXC_CCM_CSCDR1, 16, 3);
 	clk[IMX5_CLK_ESDHC_A_PODF]	=3D imx_clk_divider("esdhc_a_podf", "esdhc_a_=
pred", MXC_CCM_CSCDR1, 11, 3);
 	clk[IMX5_CLK_ESDHC_B_PRED]	=3D imx_clk_divider("esdhc_b_pred", "esdhc_b_=
sel", MXC_CCM_CSCDR1, 22, 3);
 	clk[IMX5_CLK_ESDHC_B_PODF]	=3D imx_clk_divider("esdhc_b_podf", "esdhc_b_=
pred", MXC_CCM_CSCDR1, 19, 3);
-	clk[IMX5_CLK_ESDHC_C_SEL]	=3D imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1,=
 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
-	clk[IMX5_CLK_ESDHC_D_SEL]	=3D imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1,=
 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));

 	clk[IMX5_CLK_EMI_SEL]		=3D imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1,
 						emi_slow_sel, ARRAY_SIZE(emi_slow_sel));
@@ -307,10 +301,6 @@ static void __init mx5_clocks_common_init(void __iome=
m *ccm_base)
 	clk_register_clkdev(clk[IMX5_CLK_CPU_PODF], NULL, "cpu0");
 	clk_register_clkdev(clk[IMX5_CLK_GPC_DVFS], "gpc_dvfs", NULL);

-	/* Set SDHC parents to be PLL2 */
-	clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);
-	clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]);
-
 	/* move usb phy clk to 24MHz */
 	clk_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]);
 }
@@ -347,6 +337,12 @@ static void __init mx50_clocks_init(struct device_nod=
e *np)

 	clk[IMX5_CLK_LP_APM]		=3D imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
 						lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
+	clk[IMX5_CLK_ESDHC_A_SEL]	=3D imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1,=
 21, 2,
+						standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
+	clk[IMX5_CLK_ESDHC_B_SEL]	=3D imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1,=
 16, 2,
+						standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
+	clk[IMX5_CLK_ESDHC_C_SEL]	=3D imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1,=
 20, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
+	clk[IMX5_CLK_ESDHC_D_SEL]	=3D imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1,=
 19, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
 	clk[IMX5_CLK_ESDHC1_PER_GATE]	=3D imx_clk_gate2("esdhc1_per_gate", "esdh=
c_a_podf", MXC_CCM_CCGR3, 2);
 	clk[IMX5_CLK_ESDHC2_PER_GATE]	=3D imx_clk_gate2("esdhc2_per_gate", "esdh=
c_c_sel", MXC_CCM_CCGR3, 6);
 	clk[IMX5_CLK_ESDHC3_PER_GATE]	=3D imx_clk_gate2("esdhc3_per_gate", "esdh=
c_b_podf", MXC_CCM_CCGR3, 10);
@@ -375,6 +371,10 @@ static void __init mx50_clocks_init(struct device_nod=
e *np)
 	clk_data.clk_num =3D ARRAY_SIZE(clk);
 	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);

+	/* Set SDHC parents to be PLL2 */
+	clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);
+	clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]);
+
 	/* set SDHC root clock to 200MHZ*/
 	clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
 	clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
@@ -429,6 +429,12 @@ static void __init mx51_clocks_init(struct device_nod=
e *np)
 						mx51_tve_sel, ARRAY_SIZE(mx51_tve_sel));
 	clk[IMX5_CLK_TVE_GATE]		=3D imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM=
_CCGR2, 30);
 	clk[IMX5_CLK_TVE_PRED]		=3D imx_clk_divider("tve_pred", "pll3_sw", MXC_C=
CM_CDCDR, 28, 3);
+	clk[IMX5_CLK_ESDHC_A_SEL]	=3D imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1,=
 20, 2,
+						standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
+	clk[IMX5_CLK_ESDHC_B_SEL]	=3D imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1,=
 16, 2,
+						standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
+	clk[IMX5_CLK_ESDHC_C_SEL]	=3D imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1,=
 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
+	clk[IMX5_CLK_ESDHC_D_SEL]	=3D imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1,=
 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
 	clk[IMX5_CLK_ESDHC1_PER_GATE]	=3D imx_clk_gate2("esdhc1_per_gate", "esdh=
c_a_podf", MXC_CCM_CCGR3, 2);
 	clk[IMX5_CLK_ESDHC2_PER_GATE]	=3D imx_clk_gate2("esdhc2_per_gate", "esdh=
c_b_podf", MXC_CCM_CCGR3, 6);
 	clk[IMX5_CLK_ESDHC3_PER_GATE]	=3D imx_clk_gate2("esdhc3_per_gate", "esdh=
c_c_sel", MXC_CCM_CCGR3, 10);
@@ -459,6 +465,10 @@ static void __init mx51_clocks_init(struct device_nod=
e *np)
 	/* set the usboh3 parent to pll2_sw */
 	clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]);

+	/* Set SDHC parents to be PLL2 */
+	clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);
+	clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]);
+
 	/* set SDHC root clock to 166.25MHZ*/
 	clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000);
 	clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000);
@@ -538,6 +548,12 @@ static void __init mx53_clocks_init(struct device_nod=
e *np)
 						mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT=
);
 	clk[IMX5_CLK_TVE_GATE]		=3D imx_clk_gate2("tve_gate", "tve_pred", MXC_CC=
M_CCGR2, 30);
 	clk[IMX5_CLK_TVE_PRED]		=3D imx_clk_divider("tve_pred", "tve_ext_sel", M=
XC_CCM_CDCDR, 28, 3);
+	clk[IMX5_CLK_ESDHC_A_SEL]	=3D imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1,=
 20, 2,
+						standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
+	clk[IMX5_CLK_ESDHC_B_SEL]	=3D imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1,=
 16, 2,
+						standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
+	clk[IMX5_CLK_ESDHC_C_SEL]	=3D imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1,=
 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
+	clk[IMX5_CLK_ESDHC_D_SEL]	=3D imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1,=
 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
 	clk[IMX5_CLK_ESDHC1_PER_GATE]	=3D imx_clk_gate2("esdhc1_per_gate", "esdh=
c_a_podf", MXC_CCM_CCGR3, 2);
 	clk[IMX5_CLK_ESDHC2_PER_GATE]	=3D imx_clk_gate2("esdhc2_per_gate", "esdh=
c_c_sel", MXC_CCM_CCGR3, 6);
 	clk[IMX5_CLK_ESDHC3_PER_GATE]	=3D imx_clk_gate2("esdhc3_per_gate", "esdh=
c_b_podf", MXC_CCM_CCGR3, 10);
@@ -600,6 +616,10 @@ static void __init mx53_clocks_init(struct device_nod=
e *np)
 	clk_data.clk_num =3D ARRAY_SIZE(clk);
 	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);

+	/* Set SDHC parents to be PLL2 */
+	clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);
+	clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]);
+
 	/* set SDHC root clock to 200MHZ*/
 	clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
 	clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
=2D-
2.20.1