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[209.132.180.67]) by mx.google.com with ESMTP id x6si17344051pgr.372.2019.03.26.23.21.50; Tue, 26 Mar 2019 23:22:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733257AbfC0GTq (ORCPT + 99 others); Wed, 27 Mar 2019 02:19:46 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:56967 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1733185AbfC0GTp (ORCPT ); Wed, 27 Mar 2019 02:19:45 -0400 X-UUID: 5789b0f9c6d14598a3387145ba9737e0-20190327 X-UUID: 5789b0f9c6d14598a3387145ba9737e0-20190327 Received: from mtkmrs01.mediatek.inc [(172.21.131.159)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 2088083322; Wed, 27 Mar 2019 14:19:40 +0800 Received: from MTKMBS01DR.mediatek.inc (172.21.101.111) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 27 Mar 2019 14:19:39 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs01dr.mediatek.inc (172.21.101.111) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 27 Mar 2019 14:19:38 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 27 Mar 2019 14:19:38 +0800 From: To: , , , CC: , , , , , , , , , Yongqiang Niu Subject: [PATCH v2 10/25] drm/mediatek: add commponent OVL0_2L Date: Wed, 27 Mar 2019 14:19:06 +0800 Message-ID: <1553667561-25447-11-git-send-email-yongqiang.niu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1553667561-25447-1-git-send-email-yongqiang.niu@mediatek.com> References: <1553667561-25447-1-git-send-email-yongqiang.niu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Yongqiang Niu This patch add commponent OVL0_2L Signed-off-by: Yongqiang Niu --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 310c0b9..19a8b06 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -227,6 +227,7 @@ static void mtk_gamma_set(struct mtk_ddp_comp *comp, static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { [MTK_DISP_OVL] = "ovl", + [MTK_DISP_OVL_2L] = "ovl_2l", [MTK_DISP_RDMA] = "rdma", [MTK_DISP_WDMA] = "wdma", [MTK_DISP_COLOR] = "color", @@ -266,6 +267,7 @@ struct mtk_ddp_comp_match { [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, NULL }, [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, NULL }, + [DDP_COMPONENT_OVL0_2L] = { MTK_DISP_OVL_2L, 0, NULL }, [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index 87ef290..c061784 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -25,6 +25,7 @@ enum mtk_ddp_comp_type { MTK_DISP_OVL, + MTK_DISP_OVL_2L, MTK_DISP_RDMA, MTK_DISP_WDMA, MTK_DISP_COLOR, @@ -58,6 +59,7 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_OD0, DDP_COMPONENT_OD1, DDP_COMPONENT_OVL0, + DDP_COMPONENT_OVL0_2L, DDP_COMPONENT_OVL1, DDP_COMPONENT_PWM0, DDP_COMPONENT_PWM1, -- 1.8.1.1.dirty