Received: by 2002:ac0:bc90:0:0:0:0:0 with SMTP id a16csp5115960img; Wed, 27 Mar 2019 02:20:44 -0700 (PDT) X-Google-Smtp-Source: APXvYqzFWf1Iq+61ezO4n6ctdUDDi/l3RVGO+oLyOeFWSnU6BZXSkav1Fps9fvL65m0NQYd5sDPm X-Received: by 2002:a62:480d:: with SMTP id v13mr34846024pfa.125.1553678444401; Wed, 27 Mar 2019 02:20:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553678444; cv=none; d=google.com; s=arc-20160816; b=pvG/YN06prFcJSNDPXLENdzbBMGKKmaFhUrV/u5peIyGXCphrKzHJofgqs3L5JJaW3 5OUucFcPDJXtN6wYfjLo7EoGPp05C1tPJ7bDYhsvggkuP0XmrqJ2SZc+gltL1nhfgGur N0K4cULYu6tkA8WJHXnUy461xKo6XeEXtwFkledKCARl+L4kl6FWwlFcy6PcROABMLOi v9YVXKYWrQyVD2z8t8jLYA1f1c+Y/5wlQaSaBF9i1cTYa8ohzTJvWc00M/ZCDB7/hXQE Iu+IOOOElAyBGQie/qFnE9QRPOhTBQaHU7Rm28kxla4Ba2UdTWyDURQgu4YnVTlKkAmB /cKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from; bh=lTNzOm6sf18eS/ar9i2igEw5Q6njkCZLqQu7srqpJxc=; b=oFo59xvtT5V3j3WGj2TuGuClxsaHZ0dveYF9GeShroyShgCPmtFhgWEcEhb0mHs4wU T9ptSWg6AF+IU981zskUHzZfUtBFnscfkOwq7D+i0IE7FmHwcfWWKuXcAiPaDcSQ1owS IVGJjdhYsH+0c3LaZvVzBYNcL39RirtuoIGi/lL9kqecsgf2mqguaQP2A+29X07u37e5 SfsJxdOtf0Kn+DJtocsEsUJFAavUvX3chE7W4shH2njh9fGXkXrDrRPZwUL2zIxr8AiX nZh/SpAWzXstj+rTO5LsznR1Q2CCbJysrx31rsl/PnIPmwGniRxxnFsq9tjdoDaomqrR QZHQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v2si12299825pgh.356.2019.03.27.02.20.29; Wed, 27 Mar 2019 02:20:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732177AbfC0JTl (ORCPT + 99 others); Wed, 27 Mar 2019 05:19:41 -0400 Received: from mailgw02.mediatek.com ([1.203.163.81]:8068 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725768AbfC0JTl (ORCPT ); Wed, 27 Mar 2019 05:19:41 -0400 X-UUID: f7ad7a33b819458eb1713cebf3cc2688-20190327 X-UUID: f7ad7a33b819458eb1713cebf3cc2688-20190327 Received: from mtkcas32.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 1943863941; Wed, 27 Mar 2019 17:19:37 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS33N1.mediatek.inc (172.27.4.75) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 27 Mar 2019 17:19:35 +0800 Received: from mszsdclx1067.gcn.mediatek.inc (172.27.4.253) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 27 Mar 2019 17:19:34 +0800 From: wangyan wang To: Michael Turquette , Stephen Boyd , CK Hu CC: wangyan wang , Matthias Brugger , Philipp Zabel , David Airlie , Daniel Vetter , chunhui dai , Colin Ian King , Sean Wang , Ryder Lee , , , , , , Subject: [PATCH V7 0/6] make mt7623 clock of hdmi stable Date: Wed, 27 Mar 2019 17:19:23 +0800 Message-ID: <20190327091929.73162-1-wangyan.wang@mediatek.com> X-Mailer: git-send-email 2.14.1 MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Wangyan Wang V7 adopt maintainer's suggestion. Here is the change list between V6 & V7 1. use readl directly & delete hdmi_phy->pll_rate in mtk_hdmi_pll_recalc_rate(). in "drm/mediatek: recalculate hdmi ..." 2. detele mtk_hdmi_phy_read() in mtk_hdmi_phy.c. in "fix the rate of parent for hdmi phy in MT2701" 3. optimize mtk_hdmi_pll_round_rate(). in "fix the rate of parent for hdmi phy in MT2701" chunhui dai (6): drm/mediatek: recalculate hdmi phy clock of MT2701 by querying hardware drm/mediatek: move the setting of fixed divider drm/mediatek: using different flags of clk for HDMI phy drm/mediatek: fix the rate and divder of hdmi phy for MT2701 drm/mediatek: using new factor for tvdpll in MT2701 drm/mediatek: fix the rate of parent for hdmi phy in MT2701 drivers/gpu/drm/mediatek/mtk_dpi.c | 8 ++--- drivers/gpu/drm/mediatek/mtk_hdmi_phy.c | 35 +++--------------- drivers/gpu/drm/mediatek/mtk_hdmi_phy.h | 6 +--- drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 50 ++++++++++++++++++++++---- drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 23 ++++++++++++ 5 files changed, 76 insertions(+), 46 deletions(-) -- 2.14.1