Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
From:   <Kavyasree.Kotagiri@microchip.com>
To:     <andrew@lunn.ch>, <f.fainelli@gmail.com>, <hkallweit1@gmail.com>,
        <davem@davemloft.net>
CC:     <netdev@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <Kavyasree.Kotagiri@microchip.com>
Subject: [PATCH v1 0/2] net: phy: mscc: Improvements to VSC8514 PHY driver
Thread-Topic: [PATCH v1 0/2] net: phy: mscc: Improvements to VSC8514 PHY
 driver
Thread-Index: AQHU5IM7lmXAiQHE0k6mqCQ8IQzOxQ==
Date:   Wed, 27 Mar 2019 09:55:38 +0000
Message-ID: <20190327095519.6181-1-kavyasree.kotagiri@microchip.com>
Accept-Language: en-IN, en-US
Content-Language: en-US
x-ms-exchange-messagesentrepresentingtype: 1
x-mailer: git-send-email 2.17.1
x-originating-ip: [182.72.246.220]
x-ms-publictraffictype: Email
x-ms-office365-filtering-correlation-id: c6077c87-9924-487f-f729-08d6b29a5d38
x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(7168020)(4627221)(201703031133081)(201702281549075)(8990200)(5600127)(711020)(4605104)(2017052603328)(7153060)(7193020);SRVR:BY5PR11MB4054;
x-ms-traffictypediagnostic: BY5PR11MB4054:
x-microsoft-antispam-prvs: <BY5PR11MB4054449F6A89769D36178BAC92580@BY5PR11MB4054.namprd11.prod.outlook.com>
x-forefront-prvs: 0989A7979C
x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(136003)(39860400002)(396003)(376002)(346002)(366004)(199004)(43544003)(189003)(66066001)(26005)(6116002)(3846002)(97736004)(72206003)(6486002)(476003)(6506007)(486006)(52116002)(386003)(78486014)(2616005)(6436002)(14454004)(55236004)(6512007)(102836004)(256004)(305945005)(106356001)(2501003)(68736007)(186003)(81156014)(316002)(105586002)(54906003)(81166006)(110136005)(71190400001)(5660300002)(50226002)(8676002)(71200400001)(25786009)(99286004)(107886003)(2201001)(1076003)(86362001)(478600001)(36756003)(7736002)(8936002)(2906002)(4326008)(53936002);DIR:OUT;SFP:1101;SCL:1;SRVR:BY5PR11MB4054;H:BY5PR11MB4119.namprd11.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1;
received-spf: None (protection.outlook.com: microchip.com does not designate
 permitted sender hosts)
x-ms-exchange-senderadcheck: 1
x-microsoft-antispam-message-info: mcx2MAidVwYQBiQMtz7S6GJ9ufAcU646XTIsN74PYNcqR8iLYGTXim1Z64qgFH4DPgT45V7siLukohhLFSQOtt+ZZoa5fFpGA5MTpgmgUgedCXjihAAD+ixEuesLYGxx2aNeDtXhO5ARkTQ0q6kDYTRMTMzPK5lNAD7g58JpSdZK9uRHkORccFJzN5p+VRo7ou4N7s25T95q0Tuqb96Tg/VrYfkD4rCzQY8St12Jn4VfsQr4V2DXdjBOSKjCQ6tRNBYS5Vz9MmVxodi3akVsWv8hMivwRWAzWAxxkWoDu3g+W+tRmSLdhCupe3O95yS5EFXiie1Oqvxc19+GPsFCSMx1uFZFLvodZ5wjVTL2mtk4xE1VEmdO9mI0DBnArdJ9dt3DqV/me7f5wF7ZuAHumiKPhlWU6eOnTMpKdrpxBqM=
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
MIME-Version: 1.0
X-MS-Exchange-CrossTenant-Network-Message-Id: c6077c87-9924-487f-f729-08d6b29a5d38
X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Mar 2019 09:55:38.6952
 (UTC)
X-MS-Exchange-CrossTenant-fromentityheader: Hosted
X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88
X-MS-Exchange-CrossTenant-mailboxtype: HOSTED
X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR11MB4054
X-OriginatorOrg: microchip.com
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

    The VSC8514 PHY is a 4-ports PHY that is 10/100/1000BASE-T, 100BASE-FX,
    1000BASE-X, can communicate with the MAC via QSGMII.
    The MAC interface protocol for each port within QSGMII can
    be either 1000BASE-X or SGMII, if the QSGMII MAC that the VSC8514 is
    connecting to supports this functionality.
    VSC8514 also supports SGMII MAC-side autonegotiation on each individual
    port, downshifting, can set the blinking pattern of each of its 4 LEDs,
    SyncE, 1000BASE-T Ring Resiliency as well as HP Auto-MDIX detection.

    This patch series adds support for 10BASE-T, 100BASE-TX, and 1000BASE-T=
,
    QSGMII link with the MAC, downshifting, HP Auto-MDIX detection
    and blinking pattern for its 4 LEDs.

    The GPIO register bank is a set of registers that are common to all PHY=
s
    in the package. So any modification in any register of this bank affect=
s
    all PHYs of the package.

    If the PHYs haven't been reset before booting the Linux kernel and were
    configured to use interrupts for e.g. link status updates, it is
    required to clear the interrupts mask register of all PHYs before being
    able to use interrupts with any PHY. The first PHY of the package that
    will be init will take care of clearing all PHYs interrupts mask
    registers. Thus, we need to keep track of the init sequence in the
    package, if it's already been done or if it's to be done.

    Most of the init sequence of a PHY of the package is common to all PHYs
    in the package, thus we use the SMI broadcast feature which enables us
    to propagate a write in one register of one PHY to all PHYs in the same
    package.

    This patch series adds support for VSC8514 in Microsemi driver(mscc.c)=
=20
    and removes support from Vitesse driver(vitesse.c).

v1=20
- Added 0/2 file.

Kavya Sree (2):
  net: phy: mscc: add support for VSC8514 PHY
  net: phy: vitesse: Remove support for VSC8514

 drivers/net/phy/Kconfig   |   2 +-
 drivers/net/phy/mscc.c    | 381 ++++++++++++++++++++++++++++++++++++++
 drivers/net/phy/vitesse.c |  12 --
 3 files changed, 382 insertions(+), 13 deletions(-)

--=20
2.17.1